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Freescale Semiconductor Technical Data
DSP56301 Rev. 10, 7/2006
DSP56301
24-Bit Digital Signal Processor
52 6 6 3 Memory Expansion Area Triple Timer Host Interface X Data Program RAM RAM 4096 x 24 bits 2048 x 24 bits (Default) (Default) Y Data RAM 2048 x 24 bits (Default)
ESSI
SCI
Peripheral Expansion Area Address Generator Unit Six-Channel DMA Unit 24-Bit Bootstrap ROM DSP56300 Core DDB YDB XDB PDB GDB Power Management
JTAG OnCETM
24
YAB XAB PAB DAB
External Address Bus Switch External Bus Interface and I-Cache Control
The DSP56301 is intended for general-purpose digital signal processing, particularly in multimedia and telecommunication applications, such as video conferencing and cellular telephony.
Address
14
Control
24
Internal Data Bus Switch EXTAL Clock XTAL PLL 2 RESET PINIT/NMI Program Interrupt Controller Program Decode Controller MODD/IRQD MODC/IRQC MODB/IRQB MODA/IRQA Program Address Generator
External Data Bus
Data
What's New?
Rev. 10 includes the following changes:
* Removes all references to Motorola. No specifications or part numbers were changed.
Data ALU 24 x 24+56 56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter
6
Figure 1. DSP56301 Block Diagram
The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0-3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling wireless, telecommunications, and multimedia products.
(c) Freescale Semiconductor, Inc., 1996, 2006. All rights reserved.
Table of Contents
DSP56301 Features.............................................................................................................................................iii Target Applications.............................................................................................................................................iv Product Documentation ......................................................................................................................................iv
Chapter 1
Signals/Connections
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 Power ................................................................................................................................................................1-4 Ground ..............................................................................................................................................................1-4 Clock.................................................................................................................................................................1-5 Phase Lock Loop (PLL)....................................................................................................................................1-5 External Memory Expansion Port (Port A) ......................................................................................................1-6 Interrupt and Mode Control ..............................................................................................................................1-9 Host Interface (HI32)......................................................................................................................................1-10 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-16 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-18 Serial Communication Interface (SCI) ...........................................................................................................1-19 Timers .............................................................................................................................................................1-20 JTAG/OnCE Interface.....................................................................................................................................1-21 Maximum Ratings.............................................................................................................................................2-1 Absolute Maximum Ratings .............................................................................................................................2-2 Thermal Characteristics ....................................................................................................................................2-2 DC Electrical Characteristics............................................................................................................................2-2 AC Electrical Characteristics............................................................................................................................2-4 TQFP Package Description...............................................................................................................................3-2 TQFP Package Mechanical Drawing..............................................................................................................3-11 MAP-BGA Package Description ....................................................................................................................3-12 MAP-BGA Package Mechanical Drawing .....................................................................................................3-23 Thermal Design Considerations........................................................................................................................4-1 Electrical Design Considerations......................................................................................................................4-2 Power Consumption Considerations.................................................................................................................4-3 PLL Performance Issues ...................................................................................................................................4-4 Input (EXTAL) Jitter Requirements .................................................................................................................4-4
Chapter 2
Specifications
2.1 2.2 2.3 2.4 2.5
Chapter 3
Packaging
3.1 3.2 3.3 3.4
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4 4.5
Chapter A Index
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) "asserted" Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN VIL/VOL True Asserted PIN VIH/VOH False Deasserted PIN VIH/VOH True Asserted PIN VIL/VOL False Deasserted Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
DSP56301 Technical Data, Rev. 10 ii Freescale Semiconductor
DSP56301 Features
High-Performance DSP56300 Core
* 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0-3.6 V * Object code compatible with the DSP56000 core with highly parallel instruction set * Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 x 24-bit parallel MultiplierAccumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control * Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts * Direct Memory Access (DMA) with six DMA channels supporting internal and external accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-ofblock-transfer interrupts; and triggering from interrupt lines and all peripherals * Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock and output clock with skew elimination * Hardware debugging support including On-Chip Emulation (OnCETM) module, Joint Test Action Group (JTAG) Test Access Port (TAP)
Internal Peripherals
* 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers * Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) * Serial communications interface (SCI) with baud rate generator * Triple timer module * Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled
Internal Memories
* 3 K x 24-bit bootstrap ROM * 8 K x 24-bit internal RAM total * Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM Instruction Cache X Data RAM Size Y Data RAM Size Size Size
4096 x 24 bits 3072 x 24 bits 2048 x 24 bits 1024 x 24 bits 0 1024 x 24-bit 0 1024 x 24-bit 2048 x 24 bits 2048 x 24 bits 3072 x 24 bits 3072 x 24 bits 2048 x 24 bits 2048 x 24 bits 3072 x 24 bits 3072 x 24 bits
Instruction Cache
disabled enabled disabled enabled
Switch Mode
disabled disabled enabled enabled
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor iii
External Memory Expansion
* Data memory expansion to two 16 M x 24-bit word memory spaces in 24-Bit mode or two 64 K x 16-bit memory spaces in 16-Bit Compatibility mode * Program memory expansion to one 16 M x 24-bit words memory space in 24-Bit mode or 64 K x 16-bit in 16-Bit Compatibility mode * External memory expansion port * Chip Select Logic for glueless interface to SRAMs * Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Reduced Power Dissipation
* * * * Very low-power CMOS design Wait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent)
Packaging
The DSP56301 is available in a 208-pin thin quad flat pack (TQFP) or a 252-pin molded array process-ball grid array (MAP-BGA) package. Both packages are available in lead-bearing and lead-free versions.
Target Applications
Examples of target applications include: * * * * * Wireless and wireline infrastructure applications Multi-channel wireless local loop systems DSP resource boards High-speed modem banks Packet telephony
Product Documentation
The three documents listed in the following table are required for a complete description of the DSP56301 and are necessary to design properly with the part. Documentation is available from the following sources. (See the back cover for detailed information.) * * * * A local Freescale distributor A Freescale semiconductor sales office A Freescale Literature Distribution Center The World Wide Web (WWW) Table 1.
Name
DSP56300 Family Manual DSP56301 User's Manual DSP56301 Technical Data
DSP56301 Documentation
Description Order Number
DSP56300FM/AD DSP56301UM/D DSP56301
Detailed description of the DSP56300 family processor core and instruction set Detailed functional description of the DSP56301 memory configuration, operation, and register programming DSP56301 features list and physical, electrical, timing, and package specifications
DSP56301 Technical Data, Rev. 10 iv Freescale Semiconductor
Signals/Connections
1
The DSP56301 input and output signals are organized into functional groups, as shown in Table 1-1 and illustrated in Figure 1-1. The DSP56301 operates from a 3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs.
Table 1-1.
DSP56301 Functional Signal Groupings Number of Signals by Package Type TQFP
Power (VCC)1 Ground (GND)1 Clock PLL Address Bus Port A2 Data Bus Bus Control Interrupt and Mode Control Host Interface (HI32) Enhanced Synchronous Serial Interface (ESSI) Port B3 Ports C and D4 24 15 5 52 12 24 15 5 52 12 Table 1-7 Table 1-8 Table 1-9 Table 1-11 Table 1-12 and Table 1-13 Table 1-14 Table 1-15 Table 1-16 25 26 2 3 24
Functional Group
Detailed Description
MAPBGA
45 38 2 3 24 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6
Serial Communication Interface (SCI) Timer JTAG/OnCE Port Notes: 1.
Port E5
3 3 6
3 3 6
2. 3. 4. 5. 6.
The number of available power and ground signals is package-dependent. In the TQFP package specific pins are dedicated internally to device subsystems. In the MAP-BGA package, power and ground connections (except those providing PLL power) connect to internal power and ground planes, respectively. Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI32 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. Each device also includes several no connect (NC) pins. The number of NC connections is package-dependent: the TQFP has 9 NCs and the MAP-BGA has 20 NCs. Do not connect any line, component, trace, or via to these pins. See Chapter 3 for details.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-1
Signals/Connections
DSP56301
VCCP VCCQ VCCA VCCD VCCN VCCH VCCS Power Inputs : PLL Internal Logic Address Bus Data Bus Bus Control HI32 ESSI/SCI/Timer Grounds1: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI32 ESSI/SCI/Timer
1
4 6 4 2 6 2
Interrupt /Mode Control
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
PCI Bus Host Interface (HI32) Port2
Universal Bus
Port B GPIO
52
GNDP GNDP1 GNDQ GNDA GNDD GNDN GNDH GNDS EXTAL XTAL CLKOUT PCAP PINIT/NMI
See Figure 1-2 for a listing of the Host Interface/Port B Signals
4 6 4 2 6 2
Clock
Extended Synchronous Serial Interface Port 0 (ESSI0)3
3
SC[00-02] SCK0 SRD0 STD0
Port C GPIO PC[0-2] PC3 PC4 PC5 Port D GPIO PD[0-2] PD3 PD4 PD5 Port E GPIO PE0 PE1 PE2 Timer GPIO TIO0 TIO1 TIO2
PLL Extended Synchronous Serial Interface Port 1 (ESSI1)3
3
Port A
A[0-23] D[0-23] AA[0-3] RAS[0-3] RD WR BS TA BR BG BB BL CAS BCLK BCLK Notes: 1.
24 24
External Address Bus External Data Bus External Bus Control
SC[10-12] SCK1 SRD1 STD1
4
Serial Communications Interface (SCI) Port3
RXD TXD SCLK
Timers4
TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE
JTAG/OnC E Port
2. 3. 4.
Power and ground connections are shown for the TQFP package. The MAP-BGA package uses one VCCP for the PLL power input and 44 VCC pins that connect to an internal power plane. The MAPBGA package uses two ground connections for the PLL (GNDP and GNDP1) and 36 GND pins that connect to an internal ground plane. The HI32 port supports PCI and non-PCI bus configurations. Twenty-four HI32 signals can also be configured as GPIO signals (PB[0-23]). The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0-5]), Port D GPIO signals (PD[0-5]), and Port E GPIO signals (PE[0-2]), respectively. TIO[0-2] can be configured as GPIO signals.
Figure 1-1.
Signals Identified by Functional Group
DSP56301 Technical Data, Rev. 10 1-2 Freescale Semiconductor
DSP56301
PCI Bus
HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HC0/HBE0 HC1/HBE1 HC2/HBE2 HC3/HBE3 HTRDY HIRDY HDEVSEL HLOCK HPAR HPERR HGNT HREQ HSERR HSTOP HIDSEL HFRAME HCLK HAD16 HAD17 HAD18 HAD19 HAD20 HAD21 HAD22 HAD23 HAD24 HAD25 HAD26 HAD27 HAD28 HAD29 HAD30 HAD31 HRST HINTA PVCL
Universal Bus
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HA0 HA1 HA2 Tie to pull-up or VCC HDBEN HDBDR HSAK HBS HDAK HDRQ HAEN HTA HIRQ HWR/HRW HRD/HDS Tie to pull-up or VCC Tie to pull-up or VCC HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HRST HINTA Leave unconnected
Port B GPIO
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Internal disconnect Leave unconnected
Host Port (HP) Reference
HP0 HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 HP9 HP10 HP11 HP12 HP13 HP14 HP15 HP16 HP17 HP18 HP19 HP20 HP21 HP22 HP23 HP24 HP25 HP26 HP27 HP28 HP29 HP30 HP31 HP32 HP33 HP34 HP35 HP36 HP37 HP38 HP39 HP40 HP41 HP42 HP43 HP44 HP45 HP46 HP47 HP48 HP49 HP50 PVCL
Host Interface (HI32)/ Port B Signals
Note:
HPxx is a reference only and is not a signal name. GPIO references formerly designated as HIOxx have been renamed PBxx for consistency with other Freescale DSPs.
Figure 1-2.
Host Interface/Port B Detail Signal Diagram
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-3
Signals/Connections
1.1 Power
Table 1-2.
Power Name
VCCP
Power Inputs
Description
PLL Power Isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. Quiet Power Isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Address Bus Power Isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Data Bus Power Isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Bus Control Power Isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Host Power Isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. ESSI, SCI, and Timer Power Isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each other internally. On those packages, all power input except VCCP are labeled VCC.
VCCQ
VCCA
VCCD
VCCN
VCCH
VCCS
Note:
1.2 Ground
Table 1-3.
Ground Name
GNDP
Grounds
Description
PLL Ground Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. PLL Ground 1 Ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. Quiet Ground Isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Address Bus Ground Isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Data Bus Ground Isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDP1
GNDQ
GNDA
GNDD
DSP56301 Technical Data, Rev. 10 1-4 Freescale Semiconductor
Clock
Table 1-3.
Ground Name
GNDN
Grounds
Description
Bus Control Ground Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Host Ground Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. ESSI, SCI, and Timer Ground Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. These designations are package-dependent. Some packages connect all GND inputs except GNDP and GNDP1 to each other internally. On those packages, all ground connections except GNDP and GNDP1 are labeled GND.
GNDH
GNDS
Note:
1.3 Clock
Table 1-4.
Signal Name
EXTAL Input
Clock Signals
Signal Description
Type
State During Reset
Input
External Clock/Crystal Input Interfaces the internal crystal oscillator input to an external crystal or an external clock. Crystal Output Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected.
XTAL
Output
Chip-driven
1.4 Phase Lock Loop (PLL)
Table 1-5.
Signal Name
CLKOUT
Phase Lock Loop Signals
Signal Description
Clock Output Provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
Type
Output
State During Reset
Chip-driven
PCAP
Input
Input
PLL Capacitor Connects an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-5
Signals/Connections
Table 1-5.
Signal Name
PINIT/NMI Input
Phase Lock Loop Signals (Continued)
Signal Description
PLL Initial/Non-Maskable Interrupt During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET deassertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT. PINIT/NMI can tolerate 5 V.
Type
State During Reset
Input
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tristates the relevant Port A signals: A[0-23], D[0-23], AA0/RAS0-AA3/RAS3, RD, WR, BB, CAS, BCLK, and BCLK. If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to occur and then returns to the Wait mode.
1.5.1
External Address Bus
Table 1-6. External Address Bus Signals
Signal Description
Address Bus When the DSP is the bus master, A[0-23] specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0-23] do not change state when external memory spaces are not being accessed.
Signal Name
A[0-23]
Type
Output
State During Reset
Tri-stated
1.5.2
External Data Bus
Table 1-7. External Data Bus Signals
Signal Description
Data Bus When the DSP is the bus master, D[0-23] provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0-23] are tristated.
Signal Name
D[0-23]
Type
Input/Output
State During Reset
Tri-stated
DSP56301 Technical Data, Rev. 10 1-6 Freescale Semiconductor
External Memory Expansion Port (Port A)
1.5.3
External Bus Control
Table 1-8. External Bus Control Signals
Signal Description
Address Attribute or Row Address Strobe As AA, these signals function as chip selects or additional address lines. Unlike address lines, however, the AA lines do not hold their state after a read or write operation. As RAS, these signals can be used for Dynamic Random Access Memory (DRAM) interface. These signals have programmable polarity. Read Enable When the DSP is the bus master, RD is asserted to read external memory on the data bus (D[0-23]). Otherwise, RD is tri-stated. Write Enable When the DSP is the bus master, WR is asserted to write external memory on the data bus (D[0-23]). Otherwise, WR is tri-stated. Transfer Acknowledge If the DSP56301 is the bus master and there is no external bus activity, or the DSP56301 is not the bus master, the TA input is ignored. The TA input is a Data Transfer Acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2,..., infinity) can be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, asserted to enable completion of the bus cycle, and deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the Bus Control Register (BCR), whichever is longer. The BCR can set the minimum number of wait states in external bus cycles. To use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the Operating Mode Register (OMR). TA functionality cannot be used during DRAM-type accesses; otherwise improper operation may result.
Signal Name
AA0/RAS0- AA3/RAS3
Type
Output
State During Reset
Tri-stated
RD
Output
Tri-stated
WR
Output
Tri-stated
TA
Input
Ignored Input
BR
Output
Output (deasserted)
Bus Request Asserted when the DSP requests bus mastership and deasserted when the DSP no longer needs the bus. BR can be asserted or deasserted independently of whether the DSP56301 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56301 is the bus master (see the description of bus "parking" in the BB signal description). The Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under software control, even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking and tenure of each master on the same external bus. BR is affected only by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Bus Grant Must be asserted/deasserted synchronous to CLKOUT for proper operation. An external bus arbitration circuit asserts BG when the DSP56301 becomes the next bus master. When BG is asserted, the DSP56301 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution.
BG
Input
Ignored Input
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-7
Signals/Connections
Table 1-8.
Signal Name
BB
External Bus Control Signals (Continued)
Signal Description
Bus Busy Indicates that the bus is active and must be asserted and deasserted synchronous to CLKOUT. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master can keep BB asserted after ceasing bus activity, regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without re-arbitration until another device requires the bus. BB is deasserted by an "active pull-up" method (that is, BB is driven high and then released and held high by an external pull-up resistor). BB requires an external pull-up resistor.
Type
Input/ Output
State During Reset
Input
BL
Output
Driven high (deasserted)
Bus Lock--BL is asserted at the start of an external divisible Read-ModifyWrite (RMW) bus cycle, remains asserted between the read and write cycles, and is deasserted at the end of the write bus cycle. This provides an "early bus start" signal for the bus controller. BL may be used to "resource lock" an external multi-port memory for secure semaphore updates. Early deassertion provides an "early bus end" signal useful for external bus control. If the external bus is not used during an instruction cycle, BL remains deasserted until the next external indivisible RMW cycle. The only instructions that assert BL automatically are the BSET, CLR, and BCHG instructions when they are used to modify external memory. An operation can also assert BL by setting the BLH bit in the Bus Control Register. Column Address Strobe When the DSP is the bus master, DRAM uses CAS to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM Control Register is cleared, the signal is tri-stated. Bus Clock When the DSP is the bus master, BCLK is active when the OMR[ATE] is set. When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated.
CAS
Output
Tri-stated
BCLK
Output
Tri-stated
BCLK
Output
Tri-stated
DSP56301 Technical Data, Rev. 10 1-8 Freescale Semiconductor
Interrupt and Mode Control
1.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 1-9.
Signal Name
MODA Input
Interrupt and Mode Control
Signal Description
Mode Select A Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQA during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request A Internally synchronized to CLKOUT. If IRQA is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQA to exit the Wait state. If the processor is in the Stop stand-by state and IRQA is asserted, the processor exits the Stop state. These inputs are 5 V tolerant.
Type
State During Reset
Input
IRQA
Input
MODB
Input
Input
Mode Select B Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQB during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request B Internally synchronized to CLKOUT. If IRQB is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQB to exit the Wait state. If the processor is in the Stop stand-by state and IRQC is asserted, the processor will exit the Stop state. These inputs are 5 V tolerant.
IRQB
Input
MODC
Input
Input
Mode Select C Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQC during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request C Internally synchronized to CLKOUT. If IRQC is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQC to exit the Wait state. If the processor is in the Stop stand-by state and IRQC is asserted, the processor exits the Stop state. These inputs are 5 V tolerant.
IRQC
Input
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-9
Signals/Connections
Table 1-9.
Signal Name
MODD Input
Interrupt and Mode Control (Continued)
Signal Description
Mode Select D Selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input IRQD during normal instruction processing. MODA, MODB, MODC, and MODD select one of sixteen initial chip operating modes, latched into the OMR when the RESET signal is deasserted. External Interrupt Request D Internally synchronized to CLKOUT. If IRQD is asserted synchronous to CLKOUT, multiple processors can be re-synchronized using the WAIT instruction and asserting IRQD to exit the Wait state. If the processor is in the Stop stand-by state and IRQD is asserted, the processor exits the Stop state. These inputs are 5 V tolerant.
Type
State During Reset
Input
IRQD
Input
RESET
Input
Input
Reset Deassertion of RESET is internally synchronized to the clock out (CLKOUT). When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. If RESET is deasserted synchronous to CLKOUT, exact start-up timing is guaranteed, allowing multiple processors to start synchronously and operate together in "lock-step." When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after power-up. This input is 5 V tolerant.
1.7 Host Interface (HI32)
The Host Interface (HI32) provides fast parallel data to a 32-bit port directly connected to the host bus. The HI32 supports a variety of standard buses and directly connects to a PCI bus and a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
1.7.1
Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in Table 1-10.
Table 1-10.
Action
Asynchronous read of receive byte registers
Host Port Usage Considerations
Description
When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid. Do not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX) register.
Asynchronous write to transmit byte registers
DSP56301 Technical Data, Rev. 10 1-10 Freescale Semiconductor
Host Interface (HI32)
Table 1-10.
Action
Asynchronous write to host vector
Host Port Usage Considerations (Continued)
Description
Change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a stable vector.
1.7.2
Host Port Configuration
HI32 signal functions vary according to the programmed configuration of the interface as determined by the 24-bit DSP Control Register (DCTR). Refer to the DSP56301 User's Manual for details on HI32 configuration registers.
Table 1-11.
Signal Name
HAD[0-7]
Host Interface
Signal Description
Type
Input/Output
State During Reset
Tri-stated
Host Address/Data 0-7 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 0-7 of the Address/Data bus. Host Address 3-10 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 3-10 of the Address bus. Port B 0-7 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 Data Direction Register (DIRH). These inputs are 5 V tolerant.
HA[3-10]
Input
PB[0-7]
Input or Output
HAD[8-15]
Input/Output
Tri-stated
Host Address/Data 8-15 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 8-15 of the Address/Data bus. Host Data 0-7 When HI32 is programmed to interface with a universal non-PCI bus and the HI function is selected, these signals are lines 0-7 of the Data bus. Port B 8-15 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 DIRH. These inputs are 5 V tolerant.
HD[0-7]
Input/Output
PB[8-15]
Input or Output
HC[0-3]/ HBE[0-3]
Input/Output
Tri-stated
Command 0-3/Byte Enable 0-3 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 0-7 of the Address/Data bus. Host Address 0-2 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 0-2 of the Address bus. The fourth signal in this set should connect to a pull-up resistor or directly to VCC when a non-PCI bus is used.
HA[0-2]
Input
PB[16-19]
Input or Output
Port B 16-19 When the HI32 is configured as GPIO through the DCTR, these signals are individually programmed through the HI32 DIRH. These inputs are 5 V tolerant.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-11
Signals/Connections
Table 1-11.
Signal Name
HTRDY
Host Interface (Continued)
Signal Description
Host Target Ready When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Target Ready signal. Host Data Bus Enable When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Enable signal. Port B 20 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant.
Type
Input/ Output
State During Reset
Tri-stated
HDBEN
Output
PB20
Input or Output
HIRDY
Input/ Output
Tri-stated
Host Initiator Ready When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Initiator Ready signal. Host Data Bus Direction When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Direction signal. Port B 21 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant.
HDBDR
Output
PB21
Input or Output
HDEVSEL
Input/ Output
Tri-stated
Host Device Select When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Device Select signal. Host Select Acknowledge When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Select Acknowledge signal. Port B 22 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant.
HSAK
Output
PB22
Input or Output
HLOCK
Input
Tri-stated
Host Lock When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Lock signal. Host Bus Strobe When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Bus Strobe Schmitt-trigger signal. Port B 23 When the HI32 is configured as GPIO through the DCTR, this signal is individually programmed through the HI32 DIRH. This input is 5 V tolerant.
HBS
Input
PB23
Input or Output
DSP56301 Technical Data, Rev. 10 1-12 Freescale Semiconductor
Host Interface (HI32)
Table 1-11.
Signal Name
HPAR
Host Interface (Continued)
Signal Description
Host Parity When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Parity signal. Host DMA Acknowledge When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host DMA Acknowledge Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
Type
Input/ Output
State During Reset
Tri-stated
HDAK
Input
HPERR
Input/ Output
Tri-stated
Host Parity Error When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Parity Error signal. Host DMA Request When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host DMA Request output. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HDRQ
Output
HGNT
Input
Input
Host Bus Grant When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Grant signal. Host Address Enable When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Address Enable output signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HAEN
Input
HREQ
Output
Tri-stated
Host Bus Request When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Request signal. Host Transfer Acknowledge--When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Bus Enable signal. HTA can be programmed as active high or active low. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HTA
Output
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-13
Signals/Connections
Table 1-11.
Signal Name
HSERR
Host Interface (Continued)
Signal Description
Host System Error When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host System Error signal. Host Interrupt Request When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Interrupt Request signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
Type
Output, open drain
State During Reset
Tri-stated
HIRQ
Output, open drain
HSTOP
Input/ Output
Tri-stated
Host Stop When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Stop signal. Host Write/Host Read-Write When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Write/Host Read-Write Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HWR/HRW
Input
HIDSEL
Input
Input
Host Initialization Device Select When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Initialization Device Select signal. Host Read/Host Data Strobe When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Host Data Read/Host Data Strobe Schmitttrigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HRD/HDS
Input
HFRAME
Input/ Output
Tri-stated
Host Frame When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host cycle Frame signal. Non-PCI bus When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
DSP56301 Technical Data, Rev. 10 1-14 Freescale Semiconductor
Host Interface (HI32)
Table 1-11.
Signal Name
HCLK Input
Host Interface (Continued)
Signal Description
Host Clock When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Host Bus Clock input. Non-PCI bus When HI32 is programmed to interface a universal non-PCI bus and the HI function is selected, this signal must be connected to a pull-up resistor or directly to VCC. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
Type
State During Reset
Input
HAD[16-31]
Input/Output
Tri-stated
Host Address/Data 16-31 When the HI32 is programmed to interface with a PCI bus and the HI function is selected, these signals are lines 16-31 of the Address/Data bus. Host Data 8-23 When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, these signals are lines 8-23 of the Data bus. Port B When the HI32 is configured as GPIO through the DCTR, these signals are internally disconnected. These inputs are 5 V tolerant.
HD[8-23]
Input/Output
HRST
Input
Tri-stated
Hardware Reset When the HI32 is programmed to interface with a PCI bus and the HI function is selected, this is the Hardware Reset input. Hardware Reset When HI32 is programmed to interface with a universal, non-PCI bus and the HI function is selected, this is the Hardware Reset Schmitt-trigger signal. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
HRST
Input
HINTA
Output, open drain
Tri-stated
Host Interrupt A When the HI function is selected, this signal is the Interrupt A open-drain output. Port B When the HI32 is configured as GPIO through the DCTR, this signal is internally disconnected. This input is 5 V tolerant.
PVCL
Input
Input
PCI Voltage Clamp When the HI32 is programmed to interface with a PCI bus and the HI function is selected and the PCI bus uses a 3 V signal environment, connect this pin to VCC (3.3 V) to enable the high voltage clamping required by the PCI specifications. In all other cases, including a 5 V PCI signal environment, leave the input unconnected.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-15
Signals/Connections
1.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Serial Peripheral Interface (SPI).
Table 1-12.
Signal Name
SC00
Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal Description
Serial Control 0 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O Flag 0. Port C 0 The default configuration following reset is GPIO. For PC0, signal direction is controlled through the Port Directions Register (PRR0). The signal can be configured as ESSI signal SC00 through the Port Control Register (PCR0). This input is 5 V tolerant.
Type
Input or Output
State During Reset
Input
PC0
SC01
Input/Output
Input
Serial Control 1 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag 1. Port C 1 The default configuration following reset is GPIO. For PC1, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC01 through PCR0. This input is 5 V tolerant.
PC1
Input or Output
SC02
Input/Output
Input
Serial Control Signal 2 The frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2 The default configuration following reset is GPIO. For PC2, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SC02 through PCR0. This input is 5 V tolerant.
PC2
Input or Output
DSP56301 Technical Data, Rev. 10 1-16 Freescale Semiconductor
Enhanced Synchronous Serial Interface 0 (ESSI0)
Table 1-12.
Signal Name
SCK0
Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
State During Reset
Input
Type
Input/Output
Signal Description
Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes, or the transmitter only in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6 T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.
PC3
Input or Output
Port C 3 The default configuration following reset is GPIO. For PC3, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SCK0 through PCR0. This input is 5 V tolerant.
SRD0
Input/Output
Input
Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register. SRD0 is an input when data is being received. Port C 4 The default configuration following reset is GPIO. For PC4, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal SRD0 through PCR0. This input is 5 V tolerant.
PC4
Input or Output
STD0
Input/Output
Input
Serial Transmit Data Transmits data from the serial transmit shift register. STD0 is an output when data is being transmitted. Port C 5 The default configuration following reset is GPIO. For PC5, signal direction is controlled through PRR0. The signal can be configured as an ESSI signal STD0 through PCR0. This input is 5 V tolerant.
PC5
Input or Output
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-17
Signals/Connections
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-13.
Signal Name
SC10
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal Description
Serial Control 0 Selection of Synchronous or Asynchronous mode determines function. For Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is either Transmitter 1 output or Serial I/O Flag 0. Port D 0 The default configuration following reset is GPIO. For PD0, signal direction is controlled through the Port Directions Register (PRR1). The signal can be configured as an ESSI signal SC10 through the Port Control Register (PCR1). This input is 5 V tolerant.
Type
Input or Output
State During Reset
Input
PD0
SC11
Input/Output
Input
Serial Control 1 Selection of Synchronous or Asynchronous mode determines function. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag 1. Port D 1 The default configuration following reset is GPIO. For PD1, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC11 through PCR1. This input is 5 V tolerant.
PD1
Input or Output
SC12
Input/Output
Input
Serial Control Signal 2 Frame sync for both the transmitter and receiver in Synchronous mode, for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in Synchronous operation). Port D 2 The default configuration following reset is GPIO. For PD2, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SC12 through PCR1. This input is 5 V tolerant.
PD2
Input or Output
SCK1
Input/Output
Input
Serial Clock Provides the serial bit rate clock for the ESSI interface. Clock input or output can be used by the transmitter and receiver in Synchronous modes, by the transmitter only in Asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock.
PD3
Input or Output
Port D 3 The default configuration following reset is GPIO. For PD3, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SCK1 through PCR1. This input is 5 V tolerant.
DSP56301 Technical Data, Rev. 10 1-18 Freescale Semiconductor
Serial Communication Interface (SCI)
Table 1-13.
Signal Name
SRD1
Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
State During Reset
Input
Type
Input/Output
Signal Description
Serial Receive Data Receives serial data and transfers it to the ESSI receive shift register. SRD1 is an input when data is being received. Port D 4 The default configuration following reset is GPIO. For PD4, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal SRD1 through PCR1. This input is 5 V tolerant.
PD4
Input or Output
STD1
Input/Output
Input
Serial Transmit Data Transmits data from the serial transmit shift register. STD1 is an output when data is being transmitted. Port D 5 The default configuration following reset is GPIO. For PD5, signal direction is controlled through PRR1. The signal can be configured as an ESSI signal STD1 through PCR1. This input is 5 V tolerant.
PD5
Input or Output
1.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems.
Table 1-14.
Signal Name
RXD Input
Serial Communication Interface (SCI)
Signal Description
Serial Receive Data Receives byte-oriented serial data and transfers it to the SCI receive shift register. Port E 0 The default configuration following reset is GPIO. When configured as PE0, signal direction is controlled through the SCI Port Directions Register (PRR). The signal can be configured as an SCI signal RXD through the SCI Port Control Register (PCR). This input is 5 V tolerant.
Type
State During Reset
Input
PE0
Input or Output
TXD
Output
Input
Serial Transmit Data Transmits data from SCI transmit data register. Port E 1 The default configuration following reset is GPIO. When configured as PE1, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal TXD through the SCI PCR. This input is 5 V tolerant.
PE1
Input or Output
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-19
Signals/Connections
Table 1-14.
Signal Name
SCLK
Serial Communication Interface (SCI) (Continued)
Signal Description
Serial Clock Provides the input or output clock used by the transmitter and/or the receiver. Port E 2 The default configuration following reset is GPIO. For PE2, signal direction is controlled through the SCI PRR. The signal can be configured as an SCI signal SCLK through the SCI PCR. This input is 5 V tolerant.
Type
Input/Output
State During Reset
Input
PE2
Input or Output
1.11 Timers
The DSP56301 has three identical and independent timers. Each can use internal or external clocking, interrupt the DSP56301 after a specified number of events (clocks), or signal an external device after counting a specific number of internal events.
Table 1-15.
Signal Name
TIO0
Triple Timer Signals
Signal Description
Type
Input or Output
State During Reset
Input
Timer 0 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO0 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO0 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 0 Control/Status Register (TCSR0). This input is 5 V tolerant.
TIO1
Input or Output
Input
Timer 1 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO1 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 1 Control/Status Register (TCSR1). This input is 5 V tolerant.
TIO2
Input or Output
Input
Timer 2 Schmitt-Trigger Input/Output As an external event counter or in Measurement mode, TIO2 is input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is output. The default mode after reset is GPIO input. This can be changed to output or configured as a Timer Input/Output through the Timer 2 Control/Status Register (TCSR2). This input is 5 V tolerant.
DSP56301 Technical Data, Rev. 10 1-20 Freescale Semiconductor
JTAG/OnCE Interface
1.12 JTAG/OnCE Interface
Table 1-16.
Signal Name
TCK Input
JTAG/OnCE Interface
Signal Description
Test Clock A test clock signal for synchronizing JTAG test logic. This input is 5 V tolerant.
Type
State During Reset
Input
TDI
Input
Input
Test Data Input A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 5 V tolerant.
TDO
Output
Tri-stated
Test Data Output A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. This input is 5 V tolerant.
TMS
Input
Input
Test Mode Select Sequences the test controller's state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. This input is 5 V tolerant.
TRST
Input
Input
Test Reset Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up. This input is 5 V tolerant.
DE
Input/Output
Input
Debug Event Provides a way to enter Debug mode from an external command controller (as input) or to acknowledge that the chip has entered Debug mode (as output). When asserted as an input, DE causes the DSP56300 core to finish the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands from the debug serial input line. When a debug request or a breakpoint condition causes the chip to enter Debug mode, DE is asserted as an output for three clock cycles. DE has an internal pull-up resistor. DE is not a standard part of the JTAG Test Access Port (TAP) Controller. It connects to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input is 5 V tolerant.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 1-21
Signals/Connections
DSP56301 Technical Data, Rev. 10 1-22 Freescale Semiconductor
Specifications
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC).
2
The DSP56301 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs.
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-1
Specifications
2.2 Absolute Maximum Ratings
Table 2-1.
Rating1
Supply Voltage All input voltages excluding "5 V tolerant" inputs3 All "5 V tolerant" input voltages3 Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. 3.
Maximum Ratings
Symbol
VCC VIN VIN5 I TJ TSTG
Value1, 2
-0.3 to +4.0 GND - 0.3 to VCC + 0.3 GND - 0.3 to VCC + 3.95 10 -40 to +100 -55 to +150
Unit
V V V mA
C C
GND = 0 V, VCC = 3.3 V 0.3 V, TJ = -40C to +100C, CL = 50 pF Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. CAUTION: All "5 V Tolerant" input voltages cannot be more than 3.95 V greater than the supply voltage; this restriction applies to "power on," as well as during normal operation. In any case, the input voltages must not be higher than 5.75 V. "5 V Tolerant" inputs are inputs that tolerate 5 V.
2.3 Thermal Characteristics
Table 2-2.
Characteristic
Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: 1. 2. 3. 4.
Thermal Characteristics
Symbol
RJA or JA RJC or JC JT
TQFP Value
49.5 7.2 4.7
PBGA3 Value
48.4 9 5
PBGA4 Value
25.2 -- --
Unit
C/W C/W C/W
Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per JEDEC Specification JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. These are simulated values. See note 1 for test board conditions. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board.
2.4 DC Electrical Characteristics
Table 2-3.
Characteristics
Supply voltage
DC Electrical Characteristics6
Symbol
VCC
Min
3.0
Typ
3.3
Max
3.6
Unit
V
DSP56301 Technical Data, Rev. 10 2-2 Freescale Semiconductor
DC Electrical Characteristics
Table 2-3.
Characteristics
Input high voltage * D[0-23], BG, BB, TA * MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI32 pins * EXTAL8
DC Electrical Characteristics6 (Continued)
Symbol Min Typ Max Unit
VIH VIHP VIHX
2.0 2.0 0.8 x VCC
-- -- --
VCC 5.25 VCC
V V V
Input low voltage * D[0-23], BG, BB, TA, MOD1/IRQ1, RESET, PINIT * All JTAG/ESSI/SCI/Timer/HI32 pins * EXTAL8 Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage * TTL (IOH = -0.4 mA)5,7 * CMOS (IOH = -10 A)5 Output low voltage * TTL (IOL = 1.6 mA, open-drain pins IOL = 6.7 mA)5,7 * CMOS (IOL = 10 A)5 Internal supply current2: * In Normal mode * In Wait mode3 * In Stop mode4 PLL supply current Input capacitance5 Notes: 1. 2.
VIL VILP VILX IIN ITSI VOH
-0.3 -0.3 -0.3 -10 -10
-- -- -- -- --
0.8 0.8 0.2 x VCC 10 10
V V V A A
2.4 VCC - 0.01 VOL -- -- 80 MHz 102 6 100
-- --
-- --
V V
-- -- 100 MHz 127 7.5 100 1 --
0.4 0.01
V V
ICCI ICCW ICCS
-- -- -- --
-- -- -- 2.5 10
mA mA A mA pF
CIN
--
3. 4. 5. 6. 7. 8.
Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Power Consumption Considerations on page 4-3 provides a formula to compute the estimated current requirements in Normal mode. To obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.0 V at TJ = 100C. To obtain these results, all inputs must be terminated (that is, not allowed to float). To obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during Stop state. Periodically sampled and not 100 percent tested. VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF This characteristic does not apply to XTAL and PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 x VCC and the maximum VILX should be no higher than 0.1 x VCC.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-3
Specifications
2.5 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of Table 2-3. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal's transition. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. All specifications for the high impedance state are guaranteed by design.
2.5.1
Internal Clocks
Table 2-4. Internal Clocks, CLKOUT
Expression1, 2 Characteristics Symbol Min Typ
(Ef x MF)/ (PDF x DF) Ef/2
Max
--
Internal operation frequency and CLKOUT with PLL enabled
f
--
Internal operation frequency and CLKOUT with PLL disabled Internal clock and CLKOUT high period * With PLL disabled * With PLL enabled and MF 4
f
--
--
TH
-- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF
ETC --
-- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF
*
With PLL enabled and MF > 4
--
Internal clock and CLKOUT low period * With PLL disabled * With PLL enabled and MF 4
TL
-- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF
ETC --
-- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF --
*
With PLL enabled and MF > 4
--
Internal clock and CLKOUT cycle time with PLL enabled
TC
--
ETC x PDF x DF/MF 2 x ETC TC --
Internal clock and CLKOUT cycle time with PLL disabled Instruction cycle time Notes: 1. 2. ICYC
TC --
--
--
DF = Division Factor; Ef = External frequency; ETC = External clock cycle = 1/Ef; MF = Multiplication Factor; PDF = Predivision Factor; TC = Internal clock cycle See the PLL and Clock Generator section in the DSP56300 Family Manual for details on the PLL.
DSP56301 Technical Data, Rev. 10 2-4 Freescale Semiconductor
AC Electrical Characteristics
2.5.2
External Clock Operation
The DSP56301 system clock is derived from the on-chip oscillator or it is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1.
EXTAL R Note: Make sure that in the PCTL Register: * XTLD (bit 16) = 0 * If fOSC > 200 kHz, XTLR (bit 15) = 0 XTAL Suggested Component Values: fOSC = 4 MHz fOSC = 20 MHz R = 680 k 10% R = 680 k 10% C = 56 pF 20% C = 22 pF 20% Calculations were done for a 4/20 MHz crystal with the following parameters: * CLof 30/20 pF, * C0 of 7/6 pF, * series resistance of 100/20 , and * drive level of 2 mW.
C
XTAL1
C
Fundamental Frequency Crystal Oscillator
Figure 2-1.
Crystal Oscillator Circuits
If an externally supplied square wave voltage source is used, disable the internal oscillator circuit during boot-up by setting XTLD (PCTL Register bit 16 = 1--see the DSP56301 User's Manual). The external square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT.
EXTAL VILX ETH 2 4 5 CLKOUT with PLL disabled ETL 3 ETC Midpoint VIHX
Note:
The midpoint is 0.5 (VIHX + VILX).
5
7 CLKOUT with PLL enabled
6a
6b
7
Figure 2-2.
External Clock Timing
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-5
Specifications
Table 2-5.
No.
1 2
Clock Operation
80 MHz 100 MHz Min
0
Characteristics
Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) EXTAL input low1, 2 * With PLL disabled (46.7%-53.3% duty cycle6) * With PLL enabled (42.5%-57.5% duty cycle6) EXTAL cycle time2 * With PLL disabled * With PLL enabled CLKOUT change from EXTAL fall with PLL disabled a. CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)3,5 b. CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF 4, PDF 1, Ef / PDF > 15 MHz)3,5
Symbol Min
Ef 0
Max
80.0 MHz
Max
100.0 MHz
ETH
5.84 ns 5.31 ns 5.84 ns 5.31 ns 12.50 ns 12.50 ns 4.3 ns 0.0 ns
157.0 s 157.0 s 273.1 s 11.0 ns 1.8 ns
4.67 ns 4.25 ns 4.67 ns 4.25 ns 10.00 ns 10.00 ns 4.3 ns 0.0 ns
157.0 s 157.0 s 273.1 s 11.0 ns 1.8 ns
3
ETL
4
ETC
5 6
0.0 ns
1.8 ns
0.0 ns
1.8 ns
7
Instruction cycle time = ICYC = TC4 (see Table 2-4) (46.7%-53.3% duty cycle) * With PLL disabled * With PLL enabled 1. 2. 3. 4. 5. 6.
ICYC
25.0 ns 12.50 ns
8.53 s
20.0 ns 10.00 ns
8.53 s
Notes:
Measured at 50 percent of the input transition The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF. Periodically sampled and not 100 percent tested The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF. The skew is not guaranteed for any other MF value. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met.
2.5.3
Phase Lock Loop (PLL) Characteristics
Table 2-6.
Characteristics Min Max
160
PLL Characteristics
80 MHz Min
30
100 MHz Unit Max
200 MHz
Voltage Controlled Oscillator (VCO) frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP) * @ MF 4 * @ MF > 4
30
(MF x 580) - 100 MF x 830
(MF x 780) - 140 MF x 1470
(MF x 580) - 100 MF x 830
(MF x 780) - 140 MF x 1470
pF pF
Note:
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (680 x MF) - 120, for MF 4, or 1100 x MF, for MF > 4.
DSP56301 Technical Data, Rev. 10 2-6 Freescale Semiconductor
AC Electrical Characteristics
2.5.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6
80 MHz 100 MHz Unit Min Max
26.0 -- -- -- -- -- --
No.
8 9
Characteristics
Delay from RESET assertion to all pins at reset value3 Required RESET duration4 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled * Power on, internal oscillator * During STOP, XTAL disabled (PCTL Bit 16 = 0) * During STOP, XTAL enabled (PCTL Bit 16 = 1) * During normal operation Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 * Minimum * Maximum Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1 * Minimum * Maximum Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output * Minimum * Maximum Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1
Expression Min
-- 500.0 10.0 0.75 0.75 25.0 25.0
Max
26.0 -- -- -- -- -- -- ns ns s ms ms ns ns
-- 50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC
-- 625.0 12.5 1.0 1.0 31.3 31.3
10
3.25 x TC + 2.0 20.25 TC + 10.0 TC
42.6 --
-- 263.1
34.5 --
-- 212.5
ns ns
11
7.4 --
-- 12.5
5.9 --
-- 10.0
ns ns
12
3.25 x TC + 1.0 20.25 x TC + 1.0
41.6 -- 30.0 0.0 8.25 8.25
-- 258.1 -- -- -- --
33.5 -- 30.0 0.0 6.6 7.1
-- 207.5 -- -- -- --
ns ns ns ns ns ns
13 14 15 16 17
4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0
55.1 92.6 130.0
-- -- --
44.5 74.5 105.0
-- -- --
ns ns ns
18
19
80 MHz: -- 3.75 x TC + WS x TC - 12.4 100 MHz: 3.75 x TC + WS x TC - 10.94 80 MHz: -- 3.25 x TC + WS x TC - 12.4 100 MHz: 3.25 x TC + WS x TC - 10.94
Note 8 -- Note 8 Note 8
ns ns ns
20
--
Note 8
ns
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-7
Specifications
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
80 MHz 100 MHz Unit Min Max Min Max
No.
21
Characteristics
Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1 * DRAM for all WS7
Expression
*
SRAM WS = 1
*
SRAM WS = 2, 3
*
SRAM WS 4
80 MHz: (WS + 3.5) x TC - 12.4 100 MHz: (WS + 3.5) x TC - 10.94 80 MHz: (WS + 3.5) x TC - 12.4 100 MHz: (WS + 3.5) x TC - 10.94 80 MHz: (WS + 3) x TC - 12.4 100 MHz: (WS + 3) x TC - 10.94 80 MHz: (WS + 2.5) x TC - 12.4 100 MHz: (WS + 2.5) x TC - 10.94
--
Note 8 -- Note 8
ns ns ns -- Note 8 ns ns -- Note 8 ns ns -- Note 8 TC ns ns
--
Note 8
--
Note 8
--
Note 8
22 23
Synchronous interrupt setup time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state * Minimum * Maximum Duration for IRQA assertion to recover from Stop state Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay)
7.4
TC
5.9
8.25 x TC + 1.0 24.75 x TC + 5.0
116.6 -- 7.4
-- 314.4 --
83.5 -- 5.9
-- 252.5 --
ns ns ns
24 25
PLC x ETC x PDF + (128 K - PLC/2) x TC
1.6
17.0
1.3
13.6
ms
PLC x ETC x PDF + (23.75 290.6 ns 15.4 ms 0.5) x TC (9.25 0.5) x TC 109.4 121.9
232.5 ns 87.5
12.3 ms 97.5 ns
* 26
Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay)
PLC x ETC x PDF + (128K - PLC/2) x TC PLC x ETC x PDF + (20.5 0.5) x TC 5.5 x TC
17.0
--
13.6
--
ms
15.4
--
12.3
--
ms
68.8
--
55.0
--
ns
* 27
Interrupt Request Rate * HI32, ESSI, SCI, Timer * DMA * IRQ, NMI (edge trigger) * IRQ, NMI (level trigger)
12 x TC 8 x TC 8 x TC 12 x TC
-- -- -- --
150.0 100.0 100.0 150.0
-- -- -- --
120.0 80.0 80.0 120.0
ns ns ns ns
DSP56301 Technical Data, Rev. 10 2-8 Freescale Semiconductor
AC Electrical Characteristics
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing6 (Continued)
80 MHz 100 MHz Unit Min Max
75.0 87.5 25.0 37.5 --
No.
28
Characteristics
DMA Request Rate * Data read from HI32, ESSI, SCI * Data write to HI32, ESSI, SCI * Timer * IRQ, NMI (edge trigger) Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid 1.
Expression Min
-- -- -- -- 44.5
Max
60.0 70.0 20.0 30.0 -- ns ns ns ns ns
6 x TC 7 x TC 2 x TC 3 x TC 4.25 x TC + 2.0
-- -- -- -- 55.1
29
Notes:
2.
3. 4.
5. 6. 7. 8.
When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. This timing depends on several settings: * For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. * For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored). * For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL Bit 17 and Operating Mode Register Bit 6 settings. * For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. * PLC value for PLL disable is 0. * The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz = 62 s). During the stabilization period, TC, TH, and TL is not constant, and their width may vary, so timing may vary as well. Periodically sampled and not 100 percent tested. Value depends on clock source: * For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is active and valid. * For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. * When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. VCC = 3.3 V 0.3 V; TJ = -40C to +100C, CL = 50 pF. WS = number of wait states (measured in clock cycles, number of TC). Use the expression to compute a maximum value.
RESET
VIH 9 8 10
All Pins
Reset Value
A[0-23]
First Fetch
Figure 2-3.
Reset Timing
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-9
Specifications
CLKOUT
11 RESET 12
A[0-23]
Figure 2-4.
Synchronous Reset Timing
A[0-23]
First Interrupt Instruction Execution/Fetch
RD 20
WR 21
IRQA, IRQB, IRQC, IRQD, NMI
17
19
a) First Interrupt Instruction Execution
General Purpose I/O
18 IRQA, IRQB, IRQC, IRQD, NMI
b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing
DSP56301 Technical Data, Rev. 10 2-10 Freescale Semiconductor
AC Electrical Characteristics
IRQA, IRQB, IRQC, IRQD, NMI
15
IRQA, IRQB, IRQC, IRQD, NMI 16
Figure 2-6.
External Interrupt Timing (Negative Edge-Triggered)
CLKOUT
IRQA, IRQB, IRQC, IRQD, NMI
22
23
A[0-23]
Figure 2-7.
Synchronous Interrupt from Wait State Timing
RESET
VIH
13 14 VIH VIH IRQA, IRQB, IRQC, IRQD, NMI VIL VIL
MODA, MODB, MODC, MODD, PINIT
Figure 2-8.
Operating Mode Select Timing
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-11
Specifications
24
IRQA
25
A[0-23]
First Instruction Fetch
Figure 2-9.
Recovery from Stop State Using IRQA
26
IRQA
25 A[0-23] First IRQA Interrupt Instruction Fetch
Figure 2-10.
Recovery from Stop State Using IRQA Interrupt Service
A[0-23]
DMA Source Address
RD WR 29 IRQA, IRQB, IRQC, IRQD, NMI First Interrupt Instruction Execution
Figure 2-11.
External Memory Access (DMA Source) Timing
2.5.5
External Memory Expansion Port (Port A)
DSP56301 Technical Data, Rev. 10 2-12 Freescale Semiconductor
AC Electrical Characteristics
2.5.5.1 SRAM Timing
Table 2-8. SRAM Read and Write Accesses3,6
80 MHz No. Characteristics Symbol Expression1 Min
100 Address valid and AA assertion pulse width2 tRC, tWC (WS + 1) x TC - 4.0 [1 WS 3] (WS + 2) x TC - 4.0 [4 WS 7] (WS + 3) x TC - 4.0 [WS 8] 0.25 x TC - 2.0 [WS = 1] 0.75 x TC - 2.0 [2 WS 3] 1.25 x TC - 2.0 [WS 4] 1.5 x TC - 4.0 [WS = 1] WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0 [WS 4] 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 4.0 [4 WS 7] 2.25 x TC - 4.0 [WS 8] (WS + 0.75) x TC - 5.0 [WS 1] (WS + 0.25) x TC - 5.0 [WS 1] 21.0 71.0 133.5 1.1 7.4 13.6 14.8 21.0 39.8 1.1 11.6 24.1 --
100 MHz Unit Min
16.0 56.0 106.0 0.5 5.5 10.5 11.0 16.0 31.0 0.5 8.5 18.5 --
Max
-- -- -- -- -- -- -- -- -- -- -- -- 16.9
Max
-- -- -- -- -- -- -- -- -- -- -- -- 12.5 ns ns ns ns ns ns ns ns ns ns ns ns ns
101
Address and AA valid to WR assertion
tAS
102
WR assertion pulse width
tWP
103
WR deassertion to address not valid
tWR
104
Address and AA valid to input data valid RD assertion to input data valid RD deassertion to data not valid (data hold time) Address valid to WR deassertion2 Data valid to WR deassertion (data setup time) Data hold time from WR deassertion
tAA, tAC
105
tOE
--
10.6
--
7.5
ns
106
tOHZ (WS + 0.75) x TC - 4.0 [WS 1] (WS - 0.25) x TC - 3.0 [WS 1]
0.0
--
0.0
--
ns
107
tAW
17.9
--
13.5
--
ns
108
tDS (tDW)
6.4
--
4.5
--
ns
109
tDH
0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 0.75 x TC - 3.7 [WS = 1] 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 0.25 x TC + 0.2 [1 WS 3] 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] 1.25 x TC - 4.0 [1 WS 3] 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] 0.75 x TC - 4.0 [1 WS 3] 1.75 x TC - 4.0 [4 WS 7] 2.75 x TC - 4.0 [WS 8] 0.5 x TC - 4.0 [WS = 1] TC - 4.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8]
1.1 13.6 26.1 5.7 -0.6 -6.8 -- -- -- 11.6 24.1 36.6 5.4 17.9 30.4 2.3 8.5 27.3 39.8
-- -- -- -- -- -- 3.3 15.8 28.3 -- -- -- -- -- -- -- -- -- --
0.5 10.5 20.5 3.8 -1.2 -6.2 -- -- -- 8.5 18.5 28.5 3.5 13.5 23.5 1.0 6.0 21.0 31.0
-- -- -- -- -- -- 2.7 12.7 22.7 -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
110
WR assertion to data active
111
WR deassertion to data high impedance
112
Previous RD deassertion to data active (write)
113
RD deassertion time
114
WR deassertion time
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-13
Specifications
Table 2-8.
SRAM Read and Write Accesses3,6 (Continued)
80 MHz 100 MHz Unit Min Max
--
No.
Characteristics
Symbol
Expression1 Min
1.0
Max
-- ns
115
Address valid to RD assertion RD assertion pulse width RD deassertion to address not valid
0.5 x TC - 4.0 (WS + 0.25) x TC -4.0 0.25 x TC - 2.0 [1 WS 3] 1.25 x TC - 2.0 [4 WS 7] 2.25 x TC - 2.0 [WS 8] 0.25 x TC + 2.0
2.3
116 117
11.6 1.1 13.6 26.1 5.1
-- -- -- -- --
8.5 0.5 10.5 20.5 4.5
-- -- -- -- --
ns ns ns ns ns
118
TA setup before RD or WR deassertion4 TA hold after RD or WR deassertion 1. 2. 3. 4. 5. 6.
119
0
--
0
--
ns
Notes:
WS is the number of wait states specified in the BCR. Timings 100, 107 are guaranteed by design, not tested. All timings for 100 MHz are measured from 0.5 * Vcc to 0.5 * Vcc Timing 118 is relative to the deassertion edge of RD or WR even if TA remains active. Timings 110, 111, and 112, are not helpful and are not specified for 100 MHz. VCC = 3.3 V 0.3 V; TJ = -40C to +100C, CL = 50 pF
100 A[0-23] AA[0-3] 113 RD 105 WR 104 118 119 106 116 117
TA D[0-23] Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation. Data In
Figure 2-12.
SRAM Read Access
DSP56301 Technical Data, Rev. 10 2-14 Freescale Semiconductor
AC Electrical Characteristics
100 A[0-23] AA[0-3] 107 101 WR 114 RD 118 119 102 103
TA 108 D[0-23] Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation. Data Out 109
Figure 2-13.
SRAM Write Access
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-15
Specifications
2.5.5.2 DRAM Timing
The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four wait states must be used for 100 MHz operation in Page Mode DRAM. However, using the information in the appropriate table, a designer could choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, by running the chip at a slightly lower frequency (for example, 95 MHz), by using faster DRAM (if it becomes available), and by manipulating control factors such as capacitive and resistive load to improve overall system performance.
DRAM type (tRAC ns) 100
Note: This figure should be used for primary selection. For exact and detailed timings see the following tables.
80
70
60
50 40 66 80 100 120
Chip frequency (MHz)
1 Wait state 2 Wait states
Figure 2-14.
3 Wait states 4 Wait states
DRAM Page Mode Wait States Selection Guide
DSP56301 Technical Data, Rev. 10 2-16 Freescale Semiconductor
AC Electrical Characteristics
Table 2-9.
No.
131
DRAM Page Mode Timings, Two Wait States1, 2, 3, 7
80 MHz Symbol Expression Min Max
-- ns 3 x TC 2.75 x TC 1.5 x TC - 6.5 2.5 x TC - 6.5 1.75 x TC - 4.0 3.25 x TC - 4.0 1.5 x TC - 4.0 Not supported 3.5 x TC - 6.0 4.5 x TC - 6.0 6.5 x TC - 6.0 tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA 1.25 x TC - 4.0 TC - 4.0 1.75 x TC - 4.0 3 x TC - 4.0 1.25 x TC - 4 0.5 x TC - 3.7 1.5 x TC - 4.2 2.5 x TC - 4.5 2.75 x TC - 4.3 2.5 x TC - 4.3 0.25 x TC - 3.0 1.75 x TC - 4.0 TC - 4.3 2.5 x TC - 4.0 1.75 x TC - 6.5 0.75 x TC - 1.5 0.25 x TC 37.5
Characteristics
Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses
Unit
tPC tCAC tAA tOFF tRSH tRHCP tCAS
34.4 -- -- 0.0 17.9 36.6 14.8 -- 37.8 50.3 75.3 11.6 8.5 17.9 33.5 11.6 2.6 14.6 26.8 30.1 27.0 0.1 17.9 8.2 27.3 -- 0.0 7.9 --
-- 12.3 24.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15.4 -- -- 3.1
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
132 133 134 135 136 137 138
CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS BRW[1-0] = 00 BRW[1-0] = 01 BRW[1-0] = 10 BRW[1-0] = 11 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6. 7.
6
deassertion5
tCRP
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Notes:
tGZ
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for the DSP56301. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1-0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. At this time, there are no DRAMs fast enough to fit with two wait states Page mode @ 100MHz (see Table 2-14). However, DRAM speeds are approaching two-wait-state compatibility.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-17
Specifications
Table 2-10.
DRAM Page Mode Timings, Three Wait States1, 2, 3
80 MHz 100 MHz Unit Min Max
--
No.
131
Characteristics
Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses
Symbol
Expression Min
40.0
Max
-- ns
4 x TC 3.5 x TC 2 x TC - 5.7 3 x TC - 5.7
50.0
tPC tCAC tAA tOFF tRSH tRHCP tCAS tCRP
43.7 -- -- 0.0
-- 19.3 31.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25.6 -- -- 3.1
35.0 -- -- 0.0 21.0 41.0 16.0 -- 31.5 41.5 61.5 11.0 6.0 21.0 36.0 8.5 3.5 18.3 30.5 33.2 28.2 0.2 21.0 8.2 31.0 -- 0.0 6.0 --
-- 14.3 24.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 19.3 -- -- 2.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
132 133 134 135 136 137 138
CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1-0] = 00 * BRW[1-0] = 01 * BRW[1-0] = 10 * BRW[1-0] = 11 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6.
2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 Not supported 3.75 x TC - 6.0 4.75 x TC - 6.0 6.75 x TC - 6.0
27.3 52.3 21.0 -- 40.9 53.4 78.4 14.8 8.5 27.3 46.0 11.6 5.4 23.9 39.3 42.6 36.3 2.0 27.3 11.3 39.8 -- 0.0
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ
1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 4.0 0.75 x TC - 4.0 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.8 2.5 x TC - 4.0 1.25 x TC - 4.3 3.5 x TC - 4.0 2.5 x TC - 5.7
0.75 x TC - 1.5 0.25 x TC
7.9 --
Notes:
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56301. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1-0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of pageaccess. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56301 Technical Data, Rev. 10 2-18 Freescale Semiconductor
AC Electrical Characteristics
Table 2-11.
DRAM Page Mode Timings, Four Wait States1, 2, 3
80 MHz 100 MHz Unit Min Max
--
No.
131
Characteristics
Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses
Symbol
Expression Min
50.0
Max
-- ns
5 x TC 4.5 x TC 2.75 x TC - 5.7 3.75 x TC - 5.7
62.5
tPC tCAC tAA tOFF tRSH tRHCP tCAS tCRP
56.2 -- -- 0.0
-- 28.7 41.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 34.9 -- -- 3.1
45.0 -- -- 0.0 31.0 56.0 21.0 -- 36.5 46.5 66.5 16.0 6.0 31.0 46.0 8.5 8.8 28.3 40.5 43.2 33.2 0.2 31.0 8.2 41.0 -- 0.0 6.0 --
-- 21.8 31.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 26.8 -- -- 2.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
132 133 134 135 136 137 138
CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1-0] = 00 * BRW[1-0] = 01 * BRW[1-0] = 10 * BRW[1-0] = 11 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4. 5. 6.
3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 Not supported 4.25 x TC - 6.0 5.25 x TC - 6.0 7.25 x TC - 6.0
39.8 71.0 27.3 -- 47.2 59.6 84.6 21.0 8.5 39.8 58.5 11.8 11.9 36.4 51.8 55.1 42.6 1.5 39.8 11.3 52.3 -- 0.0
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ
2 x TC - 4.0 TC - 4.0 3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 3.7 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.8 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 3.25 x TC - 5.7
0.75 x TC - 1.5 0.25 x TC
7.9 --
Notes:
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56301. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 x TC for read-after-read or write-after-write sequences). BRW[1-0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. N/A = does not apply because 100 MHz requires a minimum of three wait states. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-19
Specifications
RAS 136 131 CAS 137 140 141 A[0-23] Row Add Column Address 151 145 WR 146 RD 155 150 149 D[0-23] Data Out Data Out Data Out 156 148 Column Address 144 147 142 Last Column Address 139 138 135
Figure 2-15.
DRAM Page Mode Write Accesses
RAS 136 131 CAS 137 140 Row Add Column Address 139 141 Column Address 143 WR 133 153 RD 154 D[0-23] Data In Data In 134 132 152 138 142 Last Column Address 135
A[0-23]
Data In
Figure 2-16.
DRAM Page Mode Read Accesses
DSP56301 Technical Data, Rev. 10 2-20 Freescale Semiconductor
AC Electrical Characteristics
DRAM Type (tRAC ns)
Note:
This figure should be used for primary selection. For exact and detailed timings, see the following tables.
100
80
70
60
50 40 66 80 100 120 11 Wait States 15 Wait States
Chip Frequency (MHz)
4 Wait States 8 Wait States
Figure 2-17. Table 2-12.
DRAM Out-of-Page Wait States Selection Guide
DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
80 MHz
No.
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
Characteristics3
Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion
Symbol
tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR
Expression Min
9 x TC 4.75 x TC - 6.5 2.25 x TC - 6.5 3 x TC - 6.5 112.5 -- -- -- 0.0 3.25 x TC - 4.0 5.75 x TC - 4.0 3.25 x TC - 4.0 4.75 x TC - 4.0 2.25 x TC - 4.0 2.5 x TC 2 1.75 x TC 2 4.25 x TC - 4.0 2.75 x TC - 6.0 3.25 x TC - 4.0 36.6 67.9 36.6 55.4 24.1 29.3 19.9 49.1 28.4 36.6
Unit Max
-- 52.9 21.6 31.0 -- -- -- -- -- -- 33.3 23.9 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-21
Specifications
Table 2-12.
DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (Continued)
80 MHz Characteristics3
No.
172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 Notes:
Symbol
tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
Expression Min Max
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 87.3 -- -- 3.1 1.75 x TC - 4.0 0.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 4 x TC - 4.0 2 x TC - 3.8 1.25 x TC - 3.7 0.25 x TC - 2.6 3 x TC - 4.2 5.5 x TC - 4.2 8.5 x TC - 4.5 8.75 x TC - 4.3 7.75 x TC - 4.3 4.75 x TC - 4.0 3.25 x TC - 4.0 5.75 x TC - 4.0 5.5 x TC - 4.3 1.5 x TC - 4.0 1.75 x TC - 4.0 8.5 x TC - 4.0 7.5 x TC - 6.5 17.9 5.4 36.6 67.9 46.0 21.2 11.9 0.5 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9 64.5 14.8 17.9 102.3 -- 0.0 0.75 x TC - 1.5 0.25 x TC 7.9 --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4.
The number of wait states for an out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
DSP56301 Technical Data, Rev. 10 2-22 Freescale Semiconductor
AC Electrical Characteristics
Table 2-13.
DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2
80 MHz Symbol
tRC tRAC
No.
157 158
Characteristics3
Random read or write cycle time RAS assertion to data valid (read)
100 MHz Unit Min
120.0 -- -- -- -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 36.5 38.5 13.5 3.5 48.5 73.5 56.0 26.0 13.8 -- 0.5 45.8 70.8 110.5 113.2 98.2 53.5 48.5
Expression Min
12 x TC 80 MHz: 6.25 x TC - 6.5 100 MHz: 6.25 x TC - 7.0 80 MHz: 3.75 x TC - 6.5 100 MHz: 3.75 x TC - 7.0 80 MHz: 4.5 x TC - 6.5 100 MHz: 4.5 x TC - 7.0 150.0 -- -- -- -- -- -- 0.0 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 6.0 4.25 x TC - 4.0 1.75 x TC - 4.0 0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 3.7 80 MHz: 0.25 x TC - 2.6 100 MHz: 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 49.1 92.9 61.6 74.1 42.9 27.3 17.9 67.9 49.1 49.1 17.9 5.4 61.6 92.9 71.0 33.5 17.9 0.5 -- 58.3 89.6 139.3 142.7 123.8 67.9 61.6
Max
-- 71.6 -- 40.4 -- 49.8 -- -- -- -- -- -- -- 35.3 25.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
-- -- 55.5 -- 30.5 -- 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
159
CAS assertion to data valid (read)
tCAC
160
Column address valid to data valid (read)
tAA
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179
CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion
tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH
180 181 182 183 184 185 186
CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write)
tWCH tWCR tWP tRWL tCWL tDS tDH
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-23
Specifications
Table 2-13.
DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (Continued)
80 MHz Symbol
tDHR tWCS tCSR tRPC tROH tGA
No.
187 188 189 190 191 192
Characteristics3
RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid
100 MHz Unit Min
73.5 60.7 11.0 23.5 111.0 -- -- 0.0 6.0 --
Expression Min
7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 80 MHz: 10 x TC - 6.5 100 MHz: 10 x TC - 7.0 92.9 77.0 14.8 30.4 139.8 -- -- 0.0 0.75 x TC - 1.5 0.25 x TC 9.1 --
Max
-- -- -- -- -- 118.5 -- -- -- 3.1
Max
-- -- -- -- -- -- 93.0 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns
193 194 195
RD deassertion to data not valid WR assertion to data active
3
tGZ
WR deassertion to data high impedance 1. 2. 3. 4.
Notes:
The number of wait states for an out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
Table 2-14.
DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
80 MHz Symbol
tRC tRAC
No.
157 158
Characteristics3
Random read or write cycle time RAS assertion to data valid (read)
100 MHz Unit Min
160.0 -- -- -- -- -- -- 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5
Expression Min
16 x TC 80 MHz: 8.25 x TC - 6.5 100 MHz: 8.25 x TC - 5.7 80 MHz: 4.75 x TC - 6.5 100 MHz: 4.75 x TC - 5.7 80 MHz: 5.5 x TC - 6.5 100 MHz: 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2.0 7.75 x TC - 4.0 200.0 -- -- -- -- -- -- 0.0 74.1 117.9 74.1 99.1 55.4 41.8 32.4 92.9
Max
-- 96.6 -- 52.9 -- 62.3 -- -- -- -- -- -- -- 45.8 36.4 --
Max
-- -- 76.8 -- 41.8 -- 49.3 -- -- -- -- -- -- 37.0 29.5 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
159
CAS assertion to data valid (read)
tCAC
160
Column address valid to data valid (read)
tAA
161 162 163 164 165 166 167 168 169
CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion
tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP
DSP56301 Technical Data, Rev. 10 2-24 Freescale Semiconductor
AC Electrical Characteristics
Table 2-14.
DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (Continued)
80 MHz Symbol
tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH
No.
170 171 172 173 174 175 176 177 178 179
Characteristics3
CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion
100 MHz Unit Min
56.5 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 -- 0.5 55.8 90.8 150.5 153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 -- -- 0.0 6.0 --
Expression Min
6.25 x TC - 6.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 80 MHz: 0.25 x TC - 2.6 100 MHz: 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 80 MHz: 14 x TC - 6.5 100 MHz: 14 x TC - 5.7 74.1 74.1 30.4 5.4 74.1 117.9 83.5 58.7 18.2 0.5 -- 70.8 114.6 189.3 192.6 173.8 105.4 74.1 117.9 114.5 14.8 55.4 189.8 -- -- 0.0 0.75 x TC - 1.5 0.25 x TC 9.1 --
Max
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 168.5 -- -- -- 3.1
Max
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 134.3 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
180 181 182 183 184 185 186 187 188 189 190 191 192
CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid
tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA
193 194 195
RD deassertion to data not valid3 WR assertion to data active WR deassertion to data high impedance 1. 2. 3. 4.
tGZ
Notes:
The number of wait states for an out-of-page access is specified in the DCR. The refresh period is specified in the DCR. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ. Either tRCH or tRRH must be satisfied for read cycles.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-25
Specifications
157 162 165 RAS 163 162
167 169 168 170 166 164
CAS 171 173 174 175 A[0-23] Row Address 172 177 191 WR 160 159 RD 158 192 161 D[0-23] Data In 193 178 179 Column Address 176
Figure 2-18.
DRAM Out-of-Page Read Access
DSP56301 Technical Data, Rev. 10 2-26 Freescale Semiconductor
AC Electrical Characteristics
157 162 RAS 165 163 162
167 169 170 CAS 173 171 172 168
164
166
174 176 Column Address 181 175 188 180 182
A[0-23]
Row Address
WR 184
183 RD 185 194 D[0-23] Data Out
187 186 195
Figure 2-19.
DRAM Out-of-Page Write Access
157 162 RAS 190 170 CAS 177 WR 189 165 162 163
Figure 2-20.
DRAM Refresh Access
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-27
Specifications
2.5.5.3 Synchronous Timings (SRAM)
Table 2-15. External Bus Synchronous Timings (SRAM Access)3
Expression1,2
0.25 x TC +5.2/-0.5 0.75 x TC +4.2/-1.0
4
80 MHz Min Max
8.3 13.6 5.6 -- -- -- -- 7.6 -- -- 3.6 -- -- -- 11.9 0.0 4.5 10.6 4.8 4.3
100 MHz Unit Min
2.0 6.5 -- 1.8 4.0 0.0 2.5 -- -- 2.5 -- -- 4.0 0.0 6.7 10.0 0.0 4.5 0.0 0.0 4.0 9.3 4.3 3.8
No.
196 197 198 199 200 201 202 203
Characteristics
CLKOUT high to BS assertion CLKOUT high to BS deassertion CLKOUT high to address, and AA valid CLKOUT high to address, and AA
Max
7.7 11.7 5.0 -- -- -- -- -- 6.5 -- -- 2.5 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2.6 8.4 -- 2.4 5.8 0.0
0.25 x TC + 2.5 0.25 x TC - 0.7
invalid4
TA valid to CLKOUT high (setup time) CLKOUT high to TA invalid (hold time) CLKOUT high to data out active CLKOUT high to data out valid 0.25 x TC 80 MHz: 0.25 x TC + 4.5 100 MHz: 0.25 x TC + 4.0 0.25 x TC 80 MHz: 0.25 x TC + 0.5 100 MHz: 0.25 x TC
3.1 -- -- 3.1 -- -- 5.0 0.0
204 205
CLKOUT high to data out invalid CLKOUT high to data out high impedance
206 207 208 209 210
Data in valid to CLKOUT high (setup) CLKOUT high to data in invalid (hold) CLKOUT high to RD assertion CLKOUT high to RD deassertion CLKOUT high to WR assertion2 0.5 x TC + 4.3 [WS = 1 or WS 4] [2 WS 3] maximum: 0.75 x TC + 2.5
10.4
7.6 1.3 0.0
211 Notes:
CLKOUT high to WR deassertion 1. 2. 3. 4.
WS is the number of wait states specified in the BCR. If WS > 1, WR assertion refers to the next rising edge of CLKOUT. External bus synchronous timings should be used only for reference to the clock and not for relative timings. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. Use the status of BR (See T212) to determine whether the access referenced by A[0-23] is internal or external in this mode.
DSP56301 Technical Data, Rev. 10 2-28 Freescale Semiconductor
AC Electrical Characteristics
CLKOUT A[0-23] AA[0-3]
198 199 201
200
TA 211 210 D[0-23] 208 202 RD 206 D[0-23] Data In 209 207 205 203 204 Data Out
WR
Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation.
Figure 2-21.
Synchronous Bus Timings 1 WS (BCR Controlled)
CLKOUT A[0-23] AA[0-3] 198 201 200 TA 200 211 210 203 D[0-23] 202 208 RD 206 D[0-23] Data In 207 209 Data Out 204 205
199 201
WR
Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation.
Figure 2-22.
Synchronous Bus Timings 2 WS (TA Controlled)
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-29
Specifications
2.5.5.4 Arbitration Timings
Table 2-16. Arbitration Bus Timings1.
80 MHz No. Characteristics Expression2 Min
212 213 CLKOUT high to BR assertion/deassertion3 BG asserted/deasserted to CLKOUT high (setup) CLKOUT high to BG deasserted/asserted (hold) BB deassertion to CLKOUT high (input setup) CLKOUT high to BB assertion (input hold) CLKOUT high to BB assertion (output) CLKOUT high to BB deassertion (output) BB high to BB high impedance (output) CLKOUT high to address and controls active CLKOUT high to address and controls high impedance CLKOUT high to AA active CLKOUT high to AA deassertion CLKOUT high to AA high impedance 1. 2. 3. 0.25 x TC 0.75 x TC 0.25 x TC maximum: 0.25 x TC + 4.0 0.75 x TC 1.0 5.0
100 MHz Unit Min
0.0 4.0
Max
4.5 --
Max
4.0 -- ns ns
214
0.0
--
0.0
--
ns
215 216 217 218 219 220 221
5.0 0.0 1.0 1.0 -- 3.1 --
-- -- 4.5 4.5 5.6 -- 9.4
4.0 0.0 0.0 0.0 -- 2.5 --
-- -- 4.0 4.0 4.5 -- 7.5
ns ns ns ns ns ns ns
222 223 224 Notes:
3.1 4.1 --
-- 7.1 9.4
2.5 2.0 --
-- 6.5 7.5
ns ns ns
Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an absolute value. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal accesses and asserted for external accesses.
DSP56301 Technical Data, Rev. 10 2-30 Freescale Semiconductor
AC Electrical Characteristics
CLKOUT
BR 212 213 BG 216 215 BB 220 A[0-23] RD, WR 222 AA[0-3] Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation. 217 214
Figure 2-23.
Bus Acquisition Timings
CLKOUT
BR 212 BG 213
214
219 218 BB 221 A[0-23] RD, WR 224 223 AA[0-3] Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation.
Figure 2-24.
Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared)
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-31
Specifications
CLKOUT 212 BR 214 213 BG
219 218 BB 221 A[0-23] RD, WR 224 223 AA[0-3]
Note: Address lines A[0-23] hold their state after a read or write operation. AA[0-3] do not hold their state after a read or write operation.
Figure 2-25.
Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)
2.5.5.5 Asynchronous Bus Arbitrations Timings
Table 2-17. Asynchronous Bus Arbitration Timing1,3
80 MHz No. Characteristics Expression Min
250 251 Notes: BB assertion window from BG input deassertion4 Delay from BB assertion to BG assertion4 1. 2. 3. 4. 2.5 x Tc + 5 2 x Tc + 5 -- 25
100 MHz2 Unit Min
-- 25
Max
25 --
Max
30 -- ns ns
Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode. Asynchronous Arbitration mode is recommended for operation at 100 MHz. If Asynchronous Arbitration mode is active, none of the timings in Table 2-16 is required. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the non-overlap manner shown in Figure 2-26.
DSP56301 Technical Data, Rev. 10 2-32 Freescale Semiconductor
AC Electrical Characteristics
BG1
BB 250
BG2
251
250+251
Figure 2-26.
Asynchronous Bus Arbitration Timing
The asynchronous bus arbitration is enabled by internal BB inputs and synchronization circuits on BG. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a DSP56300 part can assume mastership and assert BB, for some time after BG is deasserted. Timing 250 defines when BB can be asserted. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other DSP56300 components which are potential masters on the same bus. If BG input is asserted before that time, a situation of BG asserted, and BB deasserted, can cause another DSP56300 component to assume mastership at the same time. Therefore, a non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided.
2.5.6
Host Interface Timing
Table 2-18. Universal Bus Mode Timing Parameters
80 MHz 100 MHz Unit Min Max
-- -- -- -- -- -- -- 26.3 2.5 80 MHz: TC - 4.9 100 MHz: TC - 4.0 80 MHz: 2.5 x TC + 2.9 100 MHz: 2.5 x TC + 2.3 80 MHz: 1.5 x TC + 3.3 100 MHz: 1.5 x TC + 2.6 80 MHz: 2 x TC - 11.6 100 MHz: 2 x TC - 9.2 -- 34.1 22.1 13.4 1.7 -- 7.6 -- -- 27.3 -- 17.6 -- 10.8 -- 1.3 -- -- -- -- 6.0 2.0 -- --
No.
300 301 302 303 304 305 306 307 308 309 310 311 312 Access Cycle Time
Characteristic
Expression Min
30.0 4.6 0.0 4.6 0.0 3.3
Max
-- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3 x TC
1 1
37.5 5.8 0.0 5.8
HA[10-0], HAEN Setup to Data Strobe Assertion
HA[10-0], HAEN Valid Hold from Data Strobe Deassertion HRW Setup to HDS Assertion2
2
HRW Valid Hold from HDS Deassertion Data Strobe Deasserted Width Data Strobe Asserted Pulse HBS Asserted Pulse Width
1
0.0 4.1 80 MHz: 2.5 x TC + 1.7 100 MHz: 2.5 x TC + 1.3 32.9
Width1
HBS Assertion to Data Strobe Assertion1 HBS Assertion to Data Strobe Deassertion1 HBS Deassertion to Data Strobe Deassertion1 Data Out Valid to TA Assertion (HBS Not Used--Tied to VCC)2 Data Out Active from Read Data Strobe Assertion3
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-33
Specifications
Table 2-18.
Universal Bus Mode Timing Parameters (Continued)
80 MHz 100 MHz Unit Min Max
18.9 -- 12.0 -- -- 30.0 -- -- -- 32.2 38.0 -- 0.0
1,2
No.
313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
Characteristic
Data Out Valid from Read Data Strobe Assertion (No Wait States Inserted--HTA Asserted)3 Data Out Valid Hold from Read Data Strobe Deassertion3 Data Out High Impedance from Read Data Strobe Deassertion Data In Valid Setup to Write Data Strobe Deassertion Data In Valid Hold from Write Data Strobe
4 3
Expression Min
-- 1.3 -- 6.6 0.0 -- 2.0 2.5
Max
16.9 -- 9.6 -- -- 30.0 -- -- -- -- 15.0 -- 12.2 -- -- -- 46.5 46.5 -- -- -- 46.5 -- -- -- -- 19.6 -- 19.6 -- 19.6 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-- 1.7 -- 8.3 0.0 --
1
Deassertion4
1
HSAK Assertion from Data Strobe Assertion
HSAK Asserted Hold from Data Strobe Deassertion HTA Active from Data Strobe Assertion1,2,5
2.0 3.1 80 MHz: 2.0 x TC + 13.0 100 MHz: 2.0 x TC + 12.2 80 MHz: 2.0 x TC + 13.0 100 MHz: 2.0 x TC + 12.2 38.0
HTA Assertion from Data Strobe Assertion (HBS Not Used--Tied to VCC)1,2,5 HTA Assertion from HBS Assertion2,5 HTA Deasserted from Data Strobe Assertion1,2,5 HTA Assertion to Data Strobe Deassertion1,2
-- 32.2 17.1 -- 15.3 -- -- -- 55.9 -- 55.9 -- -- -- -- 55.9 -- -- 28.0 -- -- -- 22.2 -- 22.2 -- 22.2 -- 4.6 0.0 2.0 -- 2.0 -- 2.0 -- 2.0 25.0 25.0 15.0 -- 0.0 -- 14.0 0.0 15.0
HTA High Impedance from Data Strobe Deassertion HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
-- (LT + 1) x TC - 6.0
7
19.0 0.0
Data Strobe Deasserted Hold from HIRQ Deassertion (HIRH = 0)1 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)1 HIRQ Deassertion from Data Strobe Assertion (HIRH = 1, HIRD = 1)1 HIRQ High Impedance from Data Strobe Assertion (HIRH = 1, HIRD = 0)1,6 HIRQ Active from Data Strobe Deassertion (HIRH = 1, HIRD = 0)1 HIRQ Deasserted Hold from Data Strobe Deassertion1 HDRQ Asserted Hold from Data Strobe Assertion HDRQ Deassertion from Data Strobe Assertion
2 1 2 1
1.5 x TC 80 MHz: 2.5 x TC + 24.7 100 MHz: 2.5 x TC + 21.5 80 MHz: 2.5 x TC + 24.7 100 MHz: 2.5 x TC + 21.5 2.5 x TC 2.5 x TC 1.5 x TC 80 MHz: 2.5 x TC + 24.7 100 MHz: 2.5 x TC + 21.5 80 MHz: 2.5 x TC + 3.7 100 MHz: 2.5 x TC + 3.0
18.8 -- -- 31.3 31.3 18.8 -- 35.0 5.8
HDRQ2 Deasserted Hold from Data Strobe Deassertion1 HDAK Assertion to Data Strobe Assertion1 HDAK Asserted Hold from Data Strobe Deassertion
1 1
0.0 2.5 --
1
HDBEN Deasserted Hold from Data Strobe Assertion HDBEN Assertion from Data Strobe Assertion
1
HDBEN Asserted Hold from Data Strobe Deassertion HDBEN Deassertion from Data Strobe Deassertion1
2.5 --
HDBDR High Hold from Read Data Strobe Assertion HDBDR Low from Read Data Strobe Assertion HDBDR Low Hold from Read Data Strobe
3
3
2.5 -- 2.5
Deassertion3
DSP56301 Technical Data, Rev. 10 2-34 Freescale Semiconductor
AC Electrical Characteristics
Table 2-18.
Universal Bus Mode Timing Parameters (Continued)
80 MHz 100 MHz Unit Min Max
22.2 22.2
No.
345 346
Characteristic
HDBDR High from Read Data Strobe Deassertion3 HRST Assertion to Host Port Pins High Impedance2 1. 2. 3. 4. 5. 6. 7. 8.
Expression Min
-- --
Max
19.6 19.6 ns ns
-- --
Notes:
The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST are shown as active-high and HTA is shown as active low. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent with the DC specifications. "LT" is the value of the latency timer register (CLAT) as programmed by the user during self configuration. LT 1. Values are valid for VCC = 3.3 0.3V
Table 2-19.
No.
300 301 302 305 307 308 309 310 312 313 314 315 316 317 324 325 326 327 328 329 Access Cycle Time
Universal Bus Mode, Synchronous Port A Type Host Timing
80 MHz 100 MHz Unit Min
3 x TC
1
Characteristic
Expression Max
-- -- -- -- -- 7.6 -- 34.1 22.1 1.7 -- 1.7 -- 8.3 0.0 0.0
1,2
Min
30.0 4.6 0.0 3.3 2.0
Max
-- -- -- -- -- 6.0 -- -- -- 16.9 -- 9.6 -- -- -- 12.2 -- -- -- 46.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
37.5 5.8 0.0 4.1 2.5
HA[10-0], HAEN Setup to Data Strobe Assertion
HA[10-0], HAEN Valid Hold from Data Strobe Deassertion1 Data Strobe Deasserted Width HBS Asserted Pulse Width HBS Assertion to Data Strobe Assertion
1 1
80 MHz: TC - 4.9 100 MHz: TC - 4.0 80 MHz: 2.5 x TC + 2.9 100 MHz: 2.5 x TC + 2.3 80 MHz: 1.5 x TC + 3.3 100 MHz: 1.5 x TC + 2.6
--
HBS Assertion to Data Strobe Deassertion1 HBS Deassertion to Data Strobe Deassertion1 Data Out Active from Read Data Strobe Assertion3 Data Out Valid from Read Data Strobe Assertion (No Wait States Inserted--HTA Asserted)3 Data Out Valid Hold from Read Data Strobe Deassertion3 Data Out High Impedance from Read Data Strobe Data In Valid Setup to Write Data Strobe Deassertion3 Deassertion4 Deassertion4
-- 27.3 -- 17.6 -- 18.9 -- 12.0 -- -- -- 15.3 -- -- -- 55.9 -- 1.3 -- 1.3 -- 6.6 0.0 0.0 -- 4.0 0.0 15.0
Data In Valid Hold from Write Data Strobe
HTA Assertion to Data Strobe Deassertion1,2 HTA High Impedance from Data Strobe Deassertion HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1) Data Strobe Deasserted Hold from HIRQ Deassertion (HIRH = 0)1 HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)1 HIRQ Deassertion from Data Strobe Assertion (HIRH = 1, HIRD = 1)1 1.5 x TC 80 MHz: 2.5 x TC + 24.7 100 MHz: 2.5 x TC + 21.5
-- (LT + 1) x TC - 6.0
7
6.5 0.0 18.8 --
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-35
Specifications
Table 2-19.
No.
330 331 332 346 347 348
Universal Bus Mode, Synchronous Port A Type Host Timing (Continued)
80 MHz Characteristic Expression Min Max
55.9 -- 31.3 31.3 -- 4.3 7.4 -- -- 22.2 -- -- 25.0 25.0 -- 3.4 5.9 46.5 -- -- 19.6 -- --
100 MHz Unit Min Max
ns ns ns ns ns ns ns
HIRQ High Impedance from Data Strobe Assertion (HIRH = 1, HIRD = 0)1,6 HIRQ Active from Data Strobe Deassertion (HIRH = 1, HIRD = 0)1 HIRQ Deasserted Hold from Data Strobe Deassertion1 HRST Assertion to Host Port Pins High Impedance2
80 MHz: 2.5 x TC + 24.7 100 MHz: 2.5 x TC + 21.5 2.5 x TC 2.5 x TC
--
HBS Assertion to CLKOUT Rising Edge Data Strobe Deassertion to CLKOUT Rising Edge1 1. 2. 3. 4. 5. 6. 7. 8.
Notes:
The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST are shown as active-high and HTA is shown as active low. The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications. HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent with the DC specifications. "LT" is the value of the latency timer register (CLAT) as programmed by the user during self configuration. Values are valid for VCC = 3.3 0.3V
HA[10-0] 301 HDS HRD HWR 302
305 307 308
HBS 309 HIRQ (HIRD = 1, HIRH = 1) 329
310 332
328 330 HIRQ (HIRD = 0, HIRH = 1)
331
Figure 2-27.
Universal Bus Mode I/O Access Timing
DSP56301 Technical Data, Rev. 10 2-36 Freescale Semiconductor
AC Electrical Characteristics
336 HDAK
337
HDS HRD HWR 305 334 335
HDRQ 333
Figure 2-28.
Universal Bus Mode DMA Access Timing
HRW 303 HDS 304
Figure 2-29.
HRW to HDS Timing
326 HIRQ 332 HDS HRD HWR 327
Figure 2-30.
HIRQ Pulse Width (HIRH = 0)
HRST 346 HI32 Outputs
Figure 2-31.
HRST Timing
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-37
Specifications
306 HDS HRD 309 307 HBS 310 322 321 320 HTA 323 HD[23-0] 312 318 HSAK 343 342 HDBDR 339 341 344 345 313 319 311 Valid (Output) 314 315 324 325
HDBEN 338 340
Figure 2-32.
Read Timing
DSP56301 Technical Data, Rev. 10 2-38 Freescale Semiconductor
AC Electrical Characteristics
306 HDS HRD 309 307 HBS 310 322 321 320 HTA 323 HD[23-0] 318 324 Valid (Input) 316 319 317 325
HSAK
HDBDR 338 HDBEN
339
340 341
Figure 2-33.
Write Timing
CLKOUT 347 HBS
Figure 2-34.
HBS Synchronous Timing
CLKOUT 348 HDS HRD
HWR
Figure 2-35.
Data Strobe Synchronous Timing
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-39
Specifications
Table 2-20.
Characteristic10
HCLK to Signal Valid Delay--Bussed Signals HCLK to Signal Valid Delay--Point to Point Float to Active Delay Active to Float Delay Input Set Up Time to HCLK--Bussed Signals Input Set Up Time to HCLK--Point to Point Input Hold Time from HCLK Reset Active Time After Power Stable Reset Active Time After HCLK Stable Reset Active to Output Float Delay HCLK Cycle Time HCLK High Time HCLK Low Time 1. 2. 3.
PCI Mode Timing Parameters1
80 MHz Symbol Min Max
11.0 12.0 -- 28.0 -- -- -- -- -- 40.0 -- -- --
100 MHz Unit Min
2.0 2.0 2.0 -- 7.0 10.0, 12.0 0.0 1.0 100.0 -- 30.0 11.0 11.0
No.
349 350 351 352 353 354 355 356 357 358 359 360 361
Max
11.0 12.0 -- 28.0 -- -- -- -- -- 40.0 -- -- -- ns ns ns ns ns ns ns ms s ns ns ns ns
tVAL tVAL(ptp) tON tOFF tSU tSU(ptp) tH tRST tRST-CLK tRST-OFF tCYC tHIGH tLOW
2.0 2.0 2.0 -- 7.0 10.0, 12.0 0.0 1.0 100.0 -- 30.0 11.0 11.0
Notes:
For standard PCI timing, see the PCI Local Bus Specification, Rev. 2.0, especially Chapters 3 and 4. The HI32 supports these timings for a PCI bus operating at 33 MHz for a DSP clock frequency of 56 MHz and above. The DSP core operating frequency should be greater than 5/3 of the PCI bus frequency to maintain proper PCI operation. HGNT has a setup time of 10 ns. HREQ has a setup time of 12 ns.
359 361 HCLK 360 349 350 OUTPUT DELAY High Impedance OUTPUT 352 INPUT 353 355 354 351
Figure 2-36.
PCI Timing
DSP56301 Technical Data, Rev. 10 2-40 Freescale Semiconductor
AC Electrical Characteristics
POWER
HCLK 357 356 HRST 358 PCI Signals
Figure 2-37.
PCI Reset Timing
2.5.7
SCI Timing
Table 2-21.
Characteristics1
SCI Timing
80 MHz 100 MHz Unit Min Max
-- -- -- -- -- -- 25.8 32.0 -- -- -- -- -- -- -- --
No.
400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415
Symbol
tSCC2
Expression Min
80.0 30.0 30.0 8.0 15.0 50.0 -- -- 18.0 0.0 9.0 640.0 310.0 310.0 290.0 290.0
Max
-- -- -- -- -- -- 19.5 32.0 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Synchronous clock cycle Clock low period Clock high period Output data setup to clock falling edge (internal clock) Output data hold after clock rising edge (internal clock) Input data setup time before clock rising edge (internal clock) Input data not valid before clock rising edge (internal clock) Clock falling edge to output data valid (external clock) Output data hold after clock rising edge (external clock) Input data setup time before clock rising edge (external clock) Input data hold time after clock rising edge (external clock) Asynchronous clock cycle Clock low period Clock high period Output data setup to clock rising edge (internal clock) Output data hold after clock rising edge (internal clock)
8 x TC tSCC/2 - 10.0 tSCC/2 - 10.0 tSCC/4 + 0.5 x TC -17.0 tSCC/4 - 0.5 x TC tSCC/4 + 0.5 x TC + 25.0 tSCC/4 + 0.5 x TC - 5.5
100.0 40.0 40.0 14.3 18.8 56.3 -- --
TC + 8.0
20.5 0.0 9.0
tACC3
64 x TC tACC/2 - 10.0 tACC/2 - 10.0 tACC/2 - 30.0 tACC/2 - 30.0
800.0 390.0 390.0 370.0 370.0
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-41
Specifications
Table 2-21.
Characteristics1
1. 2. 3.
SCI Timing (Continued)
80 MHz 100 MHz Unit Min Max Min Max
No.
Notes:
Symbol
Expression
VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF tSCC = synchronous clock cycle time (For internal clock, tSCC is determined by the SCI clock control register and TC.) tACC = asynchronous clock cycle time; value given for 1X Clock mode (For internal clock, tACC is determined by the SCI clock control register and TC.)
400 401 SCLK (Output) 403 TXD Data Valid 405 406 RXD Data Valid 404 402
a) Internal Clock
400 401 SCLK (Input) 407 TXD 409 RXD Data Valid Data Valid 410 408 402
b) External Clock Figure 2-38. SCI Synchronous Mode Timing
DSP56301 Technical Data, Rev. 10 2-42 Freescale Semiconductor
AC Electrical Characteristics
411 412 1X SCLK (Output) 414 TXD Data Valid 415 413
Figure 2-39.
SCI Asynchronous Mode Timing
2.5.8
ESSI0/ESSI1 Timing
Table 2-22.
Characteristics4, 5, 7
ESSI Timings
80 MHz 100 MHz Min
30.0 40.0 10.0 15.0 10.0 15.0 -- -- -- -- -- -- -- -- -- -- -- -- 10.0 19.0 5.0 3.0 1.0 23.0 3.5 23.0 3.0 0.0 5.5 19.0
No.
430 431 Clock cycle1
Symbol
tSSICC
Expression Min
3 x TC 4 x TC 2 x TC - 10.0 1.5 x TC 2 x TC - 10.0 1.5 x TC 50.0 37.5 15.0 18.8 15.0 18.8 -- -- -- -- -- -- -- -- -- -- -- -- 10.0 19.0 5.0 3.0 1.0 23.0 3.5 23.0 3.0 0.0 5.5 19.0
Max
-- -- -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- --
Max
-- -- -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- --
CondUnit ition6
x ck i ck ns
Clock high period For internal clock For external clock Clock low period For internal clock For external clock RXC rising edge to FSR out (bl) high RXC rising edge to FSR out (bl) low RXC rising edge to FSR out (wr) high2 RXC rising edge to FSR out (wr) low2 RXC rising edge to FSR out (wl) high RXC rising edge to FSR out (wl) low Data in setup time before RXC (SCK in Synchronous mode) falling edge Data in hold time after RXC falling edge FSR input (bl, wr) high before RXC falling edge2 FSR input (wl) high before RXC falling edge FSR input hold time after RXC falling edge Flags input setup before RXC falling edge
ns ns ns ns x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s ns ns ns ns ns ns ns ns ns ns ns ns
432
433 434 435 436 437 438 439 440 441 442 443 444
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-43
Specifications
Table 2-22.
Characteristics4, 5, 7
Flags input hold time after RXC falling edge TXC rising edge to FST out (bl) high TXC rising edge to FST out (bl) low TXC rising edge to FST out (wr) high2 TXC rising edge to FST out (wr) low2 TXC rising edge to FST out (wl) high TXC rising edge to FST out (wl) low TXC rising edge to data out enable from high impedance TXC rising edge to Transmitter #0 drive enable assertion TXC rising edge to data out valid8 TXC rising edge to data out high impedance3 TXC rising edge to Transmitter #0 drive enable deassertion3 FST input (bl, wr) setup time before TXC falling edge2 FST input (wl) to data out enable from high impedance FST input (wl) to Transmitter #0 drive enable assertion FST input (wl) setup time before TXC falling edge FST input hold time after TXC falling edge Flag output valid after TXC rising edge
ESSI Timings (Continued)
80 MHz 100 MHz Min
6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- -- 2.5 21.0 4.0 0.0 -- --
No.
445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462
Symbol
Expression Min
6.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 21.0 -- -- 2.5 21.0 4.0 0.0 -- --
Max
-- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 20.0 10.0 31.0 16.0 34.0 20.0 -- -- 27.0 31.0 -- -- -- -- 32.0 18.0
Max
-- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 20.0 10.0 31.0 16.0 34.0 20.0 -- -- 27.0 31.0 -- -- -- -- 32.0 18.0
CondUnit ition6
x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck -- -- x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DSP56301 Technical Data, Rev. 10 2-44 Freescale Semiconductor
AC Electrical Characteristics
Table 2-22.
Characteristics4, 5, 7
1. 2.
ESSI Timings (Continued)
80 MHz 100 MHz Min Max CondUnit ition6
No.
Notes:
Symbol
Expression Min Max
3. 4. 5.
6.
7.
8.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and the ESSI control register. The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as Bit Length Frame Sync signal), until the one before the last bit clock of the first word in frame. Periodically sampled and not 100 percent tested VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) Receive Frame Sync i ck = Internal Clock x ck = External Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5 x TC).
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-45
Specifications
430 431 TXC (Input/ Output) 446 FST (Bit) Out 450 FST (Word) Out 454 452 Data Out 459 Transmitter #0 Drive Enable 457 461 FST (Bit) In 453 456 First Bit Last Bit 454 455 451 447 432
458 460 FST (Word) In 462 Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. See Note 461
Figure 2-40.
ESSI Transmitter Timing
DSP56301 Technical Data, Rev. 10 2-46 Freescale Semiconductor
AC Electrical Characteristics
430 431 RXC (Input/ Output) 433 FSR (Bit) Out 437 FSR (Word) Out 440 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In 445 443 443 First Bit Last Bit 438 434 432
Figure 2-41.
ESSI Receiver Timing
2.5.9
Timer Timing
Table 2-23. Timer Timing
80 MHz 100 MHz Unit Min Max
-- -- 12.5 --
No.
480 481 482 483
Characteristics
Expression Min
22.0 22.0 9.0 103.5
Max
-- -- 10.0 -- ns ns ns ns
TIO Low TIO High Timer setup time from TIO (Input) assertion to CLKOUT rising edge Synchronous timer delay time from CLKOUT rising edge to the external memory access address out valid caused by first interrupt instruction execution CLKOUT rising edge to TIO (Output) assertion * Minimum * Maximum
2 x TC + 2.0 2 x TC + 2.0
27.0 27.0 9.0
10.25 x TC + 1.0
129.1
484
0.5 x TC + 0.5 0.5 x TC + 19.8
9.8 --
-- 26.1
5.5 --
-- 24.8
ns ns
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-47
Specifications
Table 2-23.
Timer Timing (Continued)
80 MHz 100 MHz Unit Min Max
-- 26.1
No.
485
Characteristics
CLKOUT rising edge to TIO (Output) deassertion * Minimum * Maximum VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF
Expression Min
5.5 --
Max
-- 24.8 ns ns
0.5 x TC + 0.5 0.5 x TC + 19.8
9.8 --
Note:
TIO 480 481
Figure 2-42.
TIO Timer Event Input Restrictions
CLKOUT
TIO (Input) 482 Address 483 First Interrupt Instruction Execution
Figure 2-43.
Timer Interrupt Generation
CLKOUT
TIO (Output) 484 485
Figure 2-44.
External Pulse Generation
2.5.10 GPIO Timing
Table 2-24.
No.
490 491 492 493 494 Note:
GPIO Timing
80 MHz 100 MHz Unit Min Max
31.0 -- -- -- --
Characteristics
CLKOUT edge to GPIO out valid (GPIO out delay time) CLKOUT edge to GPIO out not valid (GPIO out hold time) GPIO In valid to CLKOUT edge (GPIO in set-up time) CLKOUT edge to GPIO in not valid (GPIO in hold time) Fetch to CLKOUT edge before GPIO change VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF
Expression Min
-- 0.0 8.5 0.0 67.5
Max
8.5 -- -- -- -- ns ns ns ns ns
-- 0.0 8.5 0.0 6.75 x TC 84.4
DSP56301 Technical Data, Rev. 10 2-48 Freescale Semiconductor
AC Electrical Characteristics
CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493
A[0-23] 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register.
Figure 2-45.
GPIO Timing
2.5.11 JTAG Timing
Table 2-25.
No.
500 501 502 503 504 505 506 507 508 509 510 511 512 513 Notes:
JTAG Timing
All frequencies Unit Min Max
22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 44.0 -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0
Characteristics1,2
TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST setup time to TCK low 1. 2.
VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-49
Specifications
501 502 TCK (Input) VIH 503 VM VIL 503 502 VM
Figure 2-46.
TCK (Input) VIL
Test Clock Input Timing Diagram
VIH 504 505
Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
Figure 2-47.
Boundary Scan (JTAG) Timing Diagram
VIH
TCK (Input) TDI TMS (Input)
VIL 508 Input Data Valid 510 509
TDO (Output) 511 TDO (Output) 510 TDO (Output)
Output Data Valid
Output Data Valid
Figure 2-48.
Test Access Port Timing Diagram
DSP56301 Technical Data, Rev. 10 2-50 Freescale Semiconductor
AC Electrical Characteristics
TCK (Input) 513 TRST (Input) 512
Figure 2-49.
TRST Timing Diagram
2.5.12 OnCE Module TimIng
Table 2-26. OnCE Module Timing
80 MHz No.
500 514 515 516 Note:
100 MHz Unit Min
0.0 25.0 -- 25.0
Characteristics
Expression Min Max
22.0 -- 98.8 --
Max
22.0 -- 85.0 -- MHz ns ns ns
TCK frequency of operation DE assertion time in order to enter Debug mode Response time when DSP56301 is executing NOP instructions from internal memory Debug acknowledge assertion time VCC = 3.3 V 0.3 V; TJ = -40C to +100 C, CL = 50 pF
1/(TC x 3), max: 22.0 MHz 1.5 x TC + 10.0 5.5 x TC + 30.0 3 x TC - 5.0
0.0 28.8 -- 47.5
DE 514 515 516
Figure 2-50.
OnCE--Debug Request
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 2-51
Specifications
DSP56301 Technical Data, Rev. 10 2-52 Freescale Semiconductor
Packaging
3
This section provides information on the available packages for the DSP56301, including diagrams of the package pinouts and tables showing how the signals discussed in Section 1 are allocated for each package. The DSP56301 is available in two package types: * * 208-pin Thin Quad Flat Pack (TQFP) 252-pin Molded Array Process-Ball Grid Array (MAP-BGA)
Note: Both packages are available in lead-bearing and lead-free versions. Switching a design from a lead-bearing package device to a lead-free package device may require a change in the board manufacturing process. The lead-free package requires a higher solder flow temperature than the lead-bearing device. Refer to Lead-Free BGA Solder Joint Assembly Evaluation (EB635) for manufacturing considerations when incorporating lead-free package devices into a design.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-1
Packaging
3.1 TQFP Package Description
Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
VCCH GNDH HAD12 HAD13 HAD14 HAD15 HC1 HGNT HCLK HRST HREQ HPAR VCCH GNDH HSERR HPERR HLOCK HSTOP HDEVS PVCL GNDH VCCH HTRDY HIRDY GNDQ VCCQ HFRAM HIDSEL HC2 HAD16 HAD17 HAD18 HAD19 GNDH VCCH HAD20 HAD21 HAD22 HAD23 HC3 HAD24 HAD25 HAD26 HAD27 GNDH VCCH HAD28 HAD29 HAD30 HAD31 MODD MODC
NC NC HAD11 HAD10 HAD9 HAD8 HC0 HAD7 HAD6 HAD5 HAD4 GNDH VCCH HAD3 HAD2 HAD1 HAD0 TIO2 TIO1 TIO0 RXD SCLK VCCS GNDS HINTA VCCQ GNDQ TXD SC12 SC11 SC10 STD1 SCK1 SRD1 SRD0 SCK0 VCCS GNDS STD0 SC00 SC01 SC02 DE TMS TCK TDI TDO TRST BS BL NC NC
157
105 105
Orientation Mark
(Top View)
1 53
NC NC MODB MODA D23 D22 D21 VCCD GNDD D20 D19 D18 D17 D16 D15 VCCD GNDD D14 D13 D12 D11 D10 D9 VCCD GNDD VCCQ GNDQ D8 D7 D6 D5 D4 D3 VCCD GNDD D2 D1 D0 A23 A22 VCCA GNDA A21 A20 A19 A18 VCCA GNDA A17 A16 NC NC
3-2
AA0 AA1 VCCN GNDN CLKOUT BCLK CAS TA PINIT RESET VCCP PCAP GNDP GNDP1 BB BG BR VCCN GNDN AA2 AA3 WR RD XTAL VCCQ EXTAL GNDQ BCLK A0 A1 GNDA VCCA A2 A3 A4 A5 GNDA VCCA A6 A7 A8 A9 GNDA VCCA A10 A11 A12 A13 GNDA VCCA A14 A15
Figure 3-1.
DSP56301 Thin Quad Flat Pack (TQFP), Top View
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor
TQFP Package Description
GNDQ HIRDY HTRDY VCCH GNDH PVCL HDEVSE HSTOP HLOCK HPERR HSERR GNDH VCCH HPAR HREQ HRST HCLK HGNT HC1 HAD15 HAD14 HAD13 HAD12 GNDH VCCH HAD16 HC2 HIDSEL
NC NC MODB MODA D23 D22 D21 VCCD GNDD D20 D19 D18 D17 D16 D15 VCCD GNDD D14 D13 D12 D11 D10 D9 VCCD GNDD VCCQ GNDQ D8 D7 D6 D5 D4 D3 VCCD GNDD D2 D1 D0 A23 A22 VCCA GNDA A21 A20 A19 A18 VCCA GNDA A17 A16 NC NC
105
HFRAME VCCQ
MODC MODD HAD31 HAD30 HAD29 HAD28 VCCH GNDH HAD27 HAD26 HAD25 HAD24 HC3 HAD23 HAD22 HAD21 HAD20 VCCH GNDH HAD19 HAD18
HAD17
Freescale Semiconductor
A15 A14 VCCA GNDA A13 A12 A11 A10 VCCA GNDA A9 A8 A7 A6 VCCA GNDA A5 A4 A3 A2 VCCA GNDA A1 A0 BCLK GNDQ EXTAL VCCQ XTAL RD WR AA3 AA2 GNDN VCCN BR BG BB GNDP1 GNDP PCAP VCCP RESET PINIT TA CAS BCLK CLKOUT GNDN VCCN AA1 AA0
Figure 3-2.
DSP56301 Thin Quad Flat Pack (TQFP), Bottom View
DSP56301 Technical Data, Rev. 10 3-3
1
53
105
157
Orientation Mark (On Top Side)
(Bottom View)
NC NC HAD11 HAD10 HAD9 HAD8 HC0 HAD7 HAD6 HAD5 HAD4 GNDH VCCH HAD3 HAD2 HAD1 HAD0 TIO2 TIO1 TIO0 RXD SCLK VCCS GNDS HINTA VCCQ GNDQ TXD SC12 SC11 SC10 STD1 SCK1 SRD1 SRD0 SCK0 VCCS GNDS STD0 SC00 SC01 SC02 DE TMS TCK TDI TDO TRST BS BL NC NC
Packaging
Table 3-1.
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DSP56301 TQFP Signal Identification by Pin Number
Pin No.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Signal Name
AA0/RAS0 AA1/RAS1 VCCN GNDN CLKOUT BCLK CAS TA PINIT/NMI RESET VCCP PCAP GNDP GNDP1 BB BG BR VCCN GNDN AA2/RAS2 AA3/RAS3 WR RD XTAL VCCQ
Signal Name
EXTAL GNDQ BCLK A0 A1 GNDA VCCA A2 A3 A4 A5 GNDA VCCA A6 A7 A8 A9 GNDA VCCA A10 A11 A12 A13 GNDA VCCA
Pin No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Signal Name
A14 A15 NC NC A16 A17 GNDA VCCA A18 A19 A20 A21 GNDA VCCA A22 A23 D0 D1 D2 GNDD VCCD D3 D4 D5 D6
DSP56301 Technical Data, Rev. 10 3-4 Freescale Semiconductor
TQFP Package Description
Table 3-1.
Pin No.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DSP56301 TQFP Signal Identification by Pin Number (Continued)
Pin No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Signal Name
D7 D8 GNDQ VCCQ GNDD VCCD D9 D10 D11 D12 D13 D14 GNDD VCCD D15 D16 D17 D18 D19 D20 GNDD VCCD D21 D22 D23
Signal Name
MODA/IRQA MODB/IRQB NC NC MODC/IRQC MODD/IRQD HAD31 or HD23 HAD30 or HD22 HAD29 or HD21 HAD28 or HD20 VCCH GNDH HAD27 or HD19 HAD26 or HD18 HAD25 or HD17 HAD24 or HD16 HC3/HBE3 or PB19 HAD23 or HD15 HAD22 or HD14 HAD21 or HD13 HAD20 or HD12 VCCH GNDH HAD19 or HD11 HAD18 or HD10
Pin No.
126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Signal Name
HAD17 or HD9 HAD16 or HD8 HC2/HBE2, HA2, or PB18 HIDSEL or HRD/HDS HFRAME VCCQ GNDQ HIRDY, HDBDR, or PB21 HTRDY, HDBEN, or PB20 VCCH GNDH PVCL HDEVSEL, HSAK, or PB22 HSTOP or HWR/HRW HLOCK, HBS, or PB23 HPERR or HDRQ HSERR or HIRQ GNDH VCCH HPAR or HDAK HREQ or HTA HRST or HRST HCLK HGNT or HAEN HC1/HBE1, HA1, or PB17
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-5
Packaging
Table 3-1.
Pin No.
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Notes: 1.
DSP56301 TQFP Signal Identification by Pin Number (Continued)
Pin No.
171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
Signal Name
HAD15, HD7, or PB15 HAD14, HD6, or PB14 HAD13, HD5, or PB13 HAD12, HD4, or PB12 GNDH VCCH NC NC HAD11, HD3, or PB11 HAD10, HD2, or PB10 HAD9, HD1, or PB9 HAD8, HD0, or PB8 HC0/HBE0, HA0, or PB16 HAD7, HA10, or PB7 HAD6, HA9, or PB6 HAD5, HA8, or PB5 HAD4, HA7, or PB4 GNDH VCCH HAD3, HA6, or PB3
Signal Name
HAD2, HA5, or PB2 HAD1, HA4, or PB1 HAD0, HA3, or PB0 TIO2 TIO1 TIO0 RXD or PE0 SCLK or PE2 VCCS GNDS HINTA VCCQ GNDQ TXD or PE1 SC12 or PD2 SC11 or PD1 SC10 or PD0 STD1 or PD5 SCK1 or PD3 SRD1 or PD4
Pin No.
191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Signal Name
SRD0 or PC4 SCK0 or PC3 VCCS GNDS STD0 or PC5 SC00 or PC0 SC01 or PC1 SC02 or PC2 DE TMS TCK TDI TDO TRST BS BL NC NC
2.
Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For example, Pin 165 is address/data line HAD6 in PCI bus mode, address line HA9 in non-PCI bus mode, or GPIO line PB6 when the GPIO function is enabled for this pin. NC stands for Not Connected. These pins are reserved for future development. Do not connect any line, component, trace, or via to these pins.
DSP56301 Technical Data, Rev. 10 3-6 Freescale Semiconductor
TQFP Package Description
Table 3-2.
Signal Name
A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A3 A4 A5 A6 A7 A8 A9 AA0 AA1 AA2
DSP56301 TQFP Signal Identification by Name
Signal Name
AA3 BB BCLK BCLK BG BL BR BS CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23
Pin No.
29 30 45 46 47 48 51 52 55 56 59 60 33 61 62 65 66 34 35 36 39 40 41 42 1 2 20
Pin No.
21 15 6 28 16 206 17 205 7 5 67 68 83 84 85 86 87 90 91 92 93 94 69 95 98 99 100
Signal Name
D3 D4 D5 D6 D7 D8 D9 DE EXTAL GNDP1 GNDA GNDA GNDA GNDA GNDA GNDA GNDD GNDD GNDD GNDD GNDH GNDH GNDH GNDH GNDH GNDH GNDN
Pin No.
72 73 74 75 76 77 82 199 26 14 31 37 43 49 57 63 70 80 88 96 112 123 136 143 155 168 4
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-7
Packaging
Table 3-2.
Signal Name
GNDN GNDP GNDQ GNDQ GNDQ GNDQ GNDQ GNDS GNDS HA0 HA1 HA10 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HAD0 HAD1 HAD10 HAD11 HAD12 HAD13
DSP56301 TQFP Signal Identification by Name (Continued)
Pin No.
19 13 27 78 132 183 183 180 194 163 150 164 128 173 172 171 170 167 166 165 173 172 160 159 154 153
Signal Name
HAD14 HAD15 HAD16 HAD17 HAD18 HAD19 HAD2 HAD20 HAD21 HAD22 HAD23 HAD24 HAD25 HAD26 HAD27 HAD28 HAD29 HAD3 HAD30 HAD31 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9
Pin No.
152 151 127 126 125 124 171 121 120 119 118 116 115 114 113 110 109 170 108 107 167 166 165 164 162 161
Signal Name
HAEN HBE0 HBE1 HBE2 HBE3 HBS HC0 HC1 HC2 HC3 HCLK HD0 HD1 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD2 HD20 HD21
Pin No.
149 163 150 128 117 140 163 150 128 117 148 162 161 125 124 121 120 119 118 116 115 114 113 160 110 109
DSP56301 Technical Data, Rev. 10 3-8 Freescale Semiconductor
TQFP Package Description
Table 3-2.
Signal Name
HD22 HD23 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HDAK HDBDR HDBEN HDEVSEL HDRQ HDS HFRAME HGNT HIDSEL HINTA HIRDY HIRQ HLOCK HPAR HPERR HRD HREQ
DSP56301 TQFP Signal Identification by Name (Continued)
Pin No.
108 107 159 154 153 152 151 127 126 145 133 134 138 141 129 130 149 129 181 133 142 140 145 141 129 146
Signal Name
HRST/HRST HRW HSAK HSERR HSTOP HTA HTRDY HWR IRQA IRQB IRQC IRQD MODA MODB MODC MODD NC NC NC NC NC NC NC NC NC NMI
Pin No.
147 139 138 142 139 146 134 139 101 102 105 106 101 102 105 106 28 53 54 103 104 157 158 207 208 9
Signal Name
PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB2 PB20 PB21 PB22 PB23 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PC0 PC1
Pin No.
173 172 160 159 154 153 152 151 163 150 128 117 171 134 133 138 140 170 167 166 165 164 162 161 196 197
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-9
Packaging
Table 3-2.
Signal Name
PC2 PC3 PC4 PC5 PCAP PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PINIT PVCL RAS0 RAS1 RAS2 RAS3 RD RESET RXD SC00 SC01 Note:
DSP56301 TQFP Signal Identification by Name (Continued)
Pin No.
198 192 191 195 12 187 186 185 189 190 188
Signal Name
SC02 SC10 SC11 SC12 SCK0 SCK1 SCLK SRD0 SRD1 STD0 STD1 TA TCK TDI TDO TIO0 TIO1 TIO2 TMS TRST TXD VCCA VCCA VCCA VCCA
Pin No.
198 187 186 185 192 189 178 191 190 195 188
Signal Name
VCCA VCCA VCCD VCCD VCCD VCCD VCCH VCCH VCCH VCCH VCCH VCCH VCCN VCCN VCCP VCCQ VCCQ VCCQ VCCQ VCCS VCCS WR XTAL
Pin No.
58 64 71 81 89 97 111 122 135 144 156 169 3 18 11 25 79 131 182 179 193
177 184 178 9 137 1 2 20 21 23 10 177 196 197
8 201 202 203 176 175 174 200 204 184 32 38 44 50
22
24
NC stands for Not Connected. These pins are reserved for future development. Do not connect any line, component, or trace to these pins.
DSP56301 Technical Data, Rev. 10 3-10 Freescale Semiconductor
TQFP Package Mechanical Drawing
3.2 TQFP Package Mechanical Drawing
G
4X Pin 1 ident 1 208
0.2 T L-M N
4X 52 TIPS 157
0.2 T L-M N C L
156
P
AB AB X X= L, M or N View Y
Plating
F
Base metal
J
3X
view Y
M B V D U
0.08 M T L-M N L B1 V1 Section AB-AB rotated 900 clockwise 208 places Notes: 1.Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2.Controlling dimension: millimeter. 3. Datum plane-H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums -L-, -M-, and -N- to be determined at datum plane -H-. 5. Dimensions S and V to be determined at seating place -T-. 6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.25 per side. Dimensions A and B do include mold mismatch and are determined at datum plane -H-. 7. Dimension d does not include dambar protrusion. Dambar protrusion shall not cause the lead width to exceed 0.35 minimum space between protrusion and adjacent lead 0.07.
DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z q q1 q2 Millimeters MIN MAX 28.00 BSC 14.00 BSC 28.00 BSC 14.00 BSC --1.60 0.05 --1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.10 0.20 30.00 BSC 15.00 BSC 0.09 0.16 30.00 REF 15.00 REF 0.20 REF 1.00 REF 0 7 0 --12 REF
52 53 104
105
N A1 S1 A S View AA C
Seating plane
4X
(2) q 0.08 T
208X
T 0.05 (W)
2X R
R1
q1 0.25 C2 Gage plane (K) C1 View AA E (Z) q
CASE 998-01 Figure 3-3.
DSP56301 Mechanical Information, 208-pin TQFP Package
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-11
Packaging
3.3 MAP-BGA Package Description
Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their pin-outs.
Top View
1 A 2 NC 3 4 5 6 7 8 9 10 11 12 13 14 15 NC 16
HAD15 HCLK
HPAR HPERR HIRDY HAD16 HAD17 HAD20 HAD23 HAD24 HAD27 HAD30 HRST HSERR HDEV HIDSEL SEL HC1
B
NC
NC
HAD14 HGNT
HC2
HAD19 HAD22 HAD25 HAD29 HAD31
NC
NC
C HAD8
HAD11 HAD12 HAD13
H HREQ HLOCK FRAME HAD18 HAD21
HC3
HAD26 MODD
NC
NC
NC
D HAD5
HAD7
HAD9 HAD10
VCC
PVCL HSTOP HTRDY
VCC
VCC
VCC
HAD28 MODC
NC
MODB
D23
E HAD2
HAD4
HAD6
HC0
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
MODA
D22
D21
F HAD1
HAD0
HAD3
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
D18
D19
D20
D17
G
TI01
RXD
TI02
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
D12
D15
D16
D14
H SCLK
HINTA
TI00
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
D11
D9
D13
D8
J SC11
SC12
TXD
SC10
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
D5
D10
D7
K STD1
SCK1
SCK0
SRD0
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
D3
D6
D4
L SRD1
STD0
SC02
SC01
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
D0
D2
D1
M SC00
DE
TDO
TMS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A19
A21
A22
A23
N
TCK
TDI
NC
BL CLK OUT CAS
TA
VCC
VCC
VCC
A1
A2
VCC
VCC
A16
A17
A20
NC
P TRST
BS
AA0
PINIT
GNDP
BG
AA3
EXTAL
A5
A8
A12
NC
A15
NC
A18
R
NC
NC
AA1
VCCP
BB
AA2
XTAL
BCLK
A3
A6
A9
A11
A14
NC
NC
T
NC
BCLK RESET PCAP
GNDP1
BR
WR
RD
A0
A4
A7
A10
A13
NC
Figure 3-4.
DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
DSP56301 Technical Data, Rev. 10 3-12 Freescale Semiconductor
MAP-BGA Package Description
Bottom View
16 15 NC 14 13 12 11 10 9 8 7 6 5 4 3 2 NC 1 A
HAD30 HAD27 HAD24 HAD23 HAD20 HAD17 HAD16 HIRDY HPERR HPAR
HCLK HAD15
NC
NC
HAD31 HAD29 HAD25 HAD22 HAD19
HC2
HIDSEL HDEV HSERR HRST SEL HC1
HGNT HAD14
NC
NC
B
NC
NC
NC
MODD HAD26
HC3
H HAD21 HAD18 FRAME HLOCK HREQ
HAD13 HAD12 HAD11
HAD8 C
D23
MODB
NC
MODC HAD28
VCC
VCC
VCC
HTRDY HSTOP PVCL
VCC
HAD10 HAD9
HAD7
HAD5 D
D21
D22
MODA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
HC0
HAD6
HAD4
HAD2 E
D17
D20
D19
D18
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
HAD3
HAD0
HAD1 F
D14
D16
D15
D12
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
TI02
RXD
TI01
G
D8
D13
D9
D11
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
TI00
HINTA
SCLK H
D7
D10
D5
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
SC10
TXD
SC12
SC11 J
D4
D6
D3
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
SRD0
SCK0
SCK1
STD1 K
D1
D2
D0
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
SC01
SC02
STD0
SRD1 L
A23
A22
A21
A19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TMS
TDO
DE
SC00 M
NC
A20
A17
A16
VCC
VCC
A2
A1
VCC
VCC
VCC
TA
BL CLK OUT CAS
NC
TDI
TCK
N
A18
NC
A15
NC
A12
A8
A5
EXTAL
AA3
BG
GNDP
PINIT
AA0
BS
TRST P
NC
NC
A14
A11
A9
A6
A3
BLCK
XTAL
AA2
BB
VCCP
AA1
NC
NC
R
NC
A13
A10
A7
A4
A0
RD
WR
BR
GNDP1
PCAP RESET BCLK
NC
T
Figure 3-5.
DSP56301 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-13
Packaging
Table 3-3.
Pin No.
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
DSP56301 MAP-BGA Signal Identification by Pin Number
Pin No.
B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4
Signal Name
NC HAD15, HD7, or PB15 HCLK HPAR or HDAK HPERR or HDRQ HIRDY, HDBDR, or PB21 HAD16 or HD8 HAD17 or HD9 HAD20 or HD12 HAD23 or HD15 HAD24 or HD16 HAD27 or HD19 HAD30 or HD22 NC NC NC HAD14, HD6, or PB14 HGNT or HAEN HRST/HRST HSERR or HIRQ HDEVSEL, HSAK, or PB22 HIDSEL or HRD/HDS HC2/HBE2, HA2, or PB18 HAD19 or HD11 HAD22 or HD14
Signal Name
HAD25 or HD17 HAD29 or HD21 HAD31 or HD23 NC NC HAD8, HD0, or PB8 HAD11, HD3, or PB11 HAD12, HD4, or PB12 HAD13, HD5, or PB13 HC1/HBE1, HA1, or PB17 HREQ or HTA HLOCK, HBS, or PB23 HFRAME HAD18 or HD10 HAD21 or HD13 HC3/HBE3 or PB19 HAD26 or HD18 MODD/IRQD NC NC NC HAD5, HA8, or PB5 HAD7, HA10, or PB7 HAD9, HD1, or PB9 HAD10, HD2, or PB10
Pin No.
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
Signal Name
VCC PVCL HSTOP or HWR/HRW HTRDY, HDBEN, or PB20 VCC VCC VCC HAD28 or HD20 MODC/IRQC NC MODB/IRQB D23 HAD2, HA5, or PB2 HAD4, HA7, or PB4 HAD6, HA9, or PB6 HC0/HBE0, HA0, or PB16 VCC VCC VCC VCC VCC VCC VCC VCC VCC
DSP56301 Technical Data, Rev. 10 3-14 Freescale Semiconductor
MAP-BGA Package Description
Table 3-3.
Pin No.
E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6
DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)
Pin No.
G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15
Signal Name
MODA/IRQA D22 D21 HAD1, HA4, or PB1 HAD0, HA3, or PB0 HAD3, HA6, or PB3 VCC VCC GND GND GND GND GND GND VCC D18 D19 D20 D17 TIO1 RXD or PE0 TIO2 VCC VCC GND
Signal Name
GND GND GND GND GND VCC D12 D15 D16 D14 SCLK or PE2 HINTA TIO0 VCC VCC GND GND GND GND GND GND VCC D11 D9 D13
Pin No.
H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8
Signal Name
D8 SC11 or PD1 SC12 or PD2 TXD or PE1 SC10 or PD0 VCC GND GND GND GND GND GND VCC VCC D5 D10 D7 STD1 or PD5 SCK1 or PD3 SCK0 or PC3 SRD0 or PC4 VCC GND GND GND
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-15
Packaging
Table 3-3.
Pin No.
K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1
DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)
Pin No.
M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10
Signal Name
GND GND GND VCC VCC D3 D6 D4 SRD1 or PD4 STD0 or PC5 SC02 or PC2 SC01 or PC1 VCC GND GND GND GND GND GND VCC VCC D0 D2 D1 SC00 or PC0
Signal Name
DE TDO TMS VCC VCC VCC VCC VCC VCC VCC VCC A19 A21 A22 A23 TCK TDI NC BL TA VCC VCC VCC A1 A2
Pin No.
N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3
Signal Name
VCC VCC A16 A17 A20 NC TRST BS AA0/RAS0 CLKOUT PINIT/NMI GNDP BG AA3/RAS3 EXTAL A5 A8 A12 NC A15 NC A18 NC NC AA1/RAS1
DSP56301 Technical Data, Rev. 10 3-16 Freescale Semiconductor
MAP-BGA Package Description
Table 3-3.
Pin No.
R4 R5 R6 R7 R8 R9 R10 R11 R12 Notes: 1.
DSP56301 MAP-BGA Signal Identification by Pin Number (Continued)
Pin No.
R13 R14 R15 R16 T2 T3 T4 T5 T6
Signal Name
CAS VCCP BB AA2/RAS2 XTAL BCLK A3 A6 A9
Signal Name
A11 A14 NC NC NC BCLK RESET PCAP GNDP1
Pin No.
T7 T8 T9 T10 T11 T12 T13 T14 T15
Signal Name
BR WR RD A0 A4 A7 A10 A13 NC
2.
Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GNDP and GNDP1 that support the PLL, other GND signals do not support individual subsystems in the chip. NC stands for Not Connected. The following pin groups are shorted to each other: -- pins A2, B1, and B2 -- pins A15, B15, B16, C14, C15, C16, and D14 -- pins N3, R1, R2, and T2 -- pins N16, P13, P15, R15, R16, and T15 Do not connect any line, component, trace, or via to these pins.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-17
Packaging
Table 3-4.
Signal Name
A0 A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A3 A4 A5 A6 A7 A8 A9 AA0 AA1
DSP56301 MAP-BGA Signal Identification by Name
Signal Name
AA2 AA3 BB BCLK BCLK BG BL BR BS CAS CLKOUT D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21
Pin No.
T10 N9 T13 R13 P12 T14 R14 P14 N13 N14 P16 M13 N10 N15 M14 M15 M16 R10 T11 P10 R11 T12 P11 R12 P3 R3
Pin No.
R7 P8 R6 T3 R9 P7 N4 T7 P2 R4 P4 L14 L16 J15 H13 G13 H15 G16 G14 G15 F16 F13 F14 L15 F15 E16
Signal Name
D22 D23 D3 D4 D5 D6 D7 D8 D9 DE EXTAL GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Pin No.
E15 D16 K14 K16 J14 K15 J16 H16 H14 M2 P9 F10 F11 F6 F7 F8 F9 G10 G11 G6 G7 G8 G9 H10 H11 H6
DSP56301 Technical Data, Rev. 10 3-18 Freescale Semiconductor
MAP-BGA Package Description
Table 3-4.
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDP1 GNDP HA0 HA1
DSP56301 MAP-BGA Signal Identification by Name (Continued)
Pin No.
H7 H8 H9 J10 J11 J6 J7 J8 J9 K10 K11 K6 K7 K8 K9 L10 L11 L6 L7 L8 L9 T6 P6 E4 C5
Signal Name
HA10 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HAD0 HAD1 HAD10 HAD11 HAD12 HAD13 HAD14 HAD15 HAD16 HAD17 HAD18 HAD19 HAD2 HAD20 HAD21 HAD22
Pin No.
D2 B9 F2 F1 E1 F3 E2 D1 E3 F2 F1 D4 C2 C3 C4 B3 A3 A8 A9 C9 B10 E1 A10 C10 B11
Signal Name
HAD23 HAD24 HAD25 HAD26 HAD27 HAD28 HAD29 HAD3 HAD30 HAD31 HAD4 HAD5 HAD6 HAD7 HAD8 HAD9 HAEN HBE0 HBE1 HBE2 HBE3 HBS HC0 HC1 HC2
Pin No.
A11 A12 B12 C12 A13 D12 B13 F3 A14 B14 E2 D1 E3 D2 C1 D3 B4 E4 C5 B9 C11 C7 E4 C5 B9
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-19
Packaging
Table 3-4.
Signal Name
HC3 HCLK HD0 HD1 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD2 HD20 HD21 HD22 HD23 HD3 HD4 HD5 HD6 HD7 HD8
DSP56301 MAP-BGA Signal Identification by Name (Continued)
Pin No.
C11 A4 C1 D3 C9 B10 A10 C10 B11 A11 A12 B12 C12 A13 D4 D12 B13 A14 B14 C2 C3 C4 B3 A3 A8
Signal Name
HD9 HDAK HDBDR HDBEN HDEVSEL HDRQ HDS HFRAME HGNT HIDSEL HINTA HIRDY HIRQ HLOCK HPAR HPERR HRD HREQ HRST/HRST HRW HSAK HSERR HSTOP HTA HTRDY
Pin No.
A9 A5 A7 D8 B7 A6 B8 C8 B4 B8 H2 A7 B6 C7 A5 A6 B8 C6 B5 D7 B7 B6 D7 C6 D8
Signal Name
HWR IRQA IRQB IRQC IRQD MODA MODB MODC MODD NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin No.
D7 E14 D15 D13 C13 E14 D15 D13 C13 A15 A2 B1 B15 B16 B2 C14 C15 C16 D14 N16 N3 P13 P15 R1 R2
DSP56301 Technical Data, Rev. 10 3-20 Freescale Semiconductor
MAP-BGA Package Description
Table 3-4.
Signal Name
NC NC NC NC NMI PB0 PB1 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB2 PB20 PB21 PB22 PB23 PB3 PB4 PB5
DSP56301 MAP-BGA Signal Identification by Name (Continued)
Pin No.
R15 R16 T2 T15 P5 F2 F1 D4 C2 C3 C4 B3 A3 E4 C5 B9 C11 E1 D8 A7 B7 C7 F3 E2 D1
Signal Name
PB6 PB7 PB8 PB9 PC0 PC1 PC2 PC3 PC4 PC5 PCAP PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PINIT PVCL RAS0 RAS1 RAS2
Pin No.
E3 D2 C1 D3 M1 L4 L3 K3 K4 L2 T5 J4 J1 J2 K2 L1 K1 G2 J3 H1 P5 D6 P3 R3 R7
Signal Name
RAS3 RD RESET RXD SC00 SC01 SC02 SC10 SC11 SC12 SCK0 SCK1 SCLK SRD0 SRD1 STD0 STD1 TA TCK TDI TDO TIO0 TIO1 TIO2 TMS
Pin No.
P8 T9 T4 G2 M1 L4 L3 J4 J1 J2 K3 K2 H1 K4 L1 L2 K1 N5 N1 N2 M3 H3 G1 G3 M4
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-21
Packaging
Table 3-4.
Signal Name
TRST TXD VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Note:
DSP56301 MAP-BGA Signal Identification by Name (Continued)
Pin No.
P1 J3 D10 D11 D5 D9 E10 E11 E12 E13 E5 E6 E7 E8 E9 F12 F4
Signal Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Pin No.
F5 G12 G4 G5 H12 H4 H5 J12 J13 J5 K12 K13 K5 L12 L13 L5
Signal Name
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP WR XTAL
Pin No.
M10 M11 M12 M5 M6 M7 M8 M9 N11 N12 N6 N7 N8 R5 T8 R8
NC stands for Not Connected. The following pin groups are shorted to each other: --pins A2, B1, and B2 --pins A15, B15, B16, C14, C15, C16, and D14 --pins N3, R1, R2, and T2 --pins N16, P13, P15, R15, R16, and T15 Do not connect any line, component, trace, or via to these pins.
DSP56301 Technical Data, Rev. 10 3-22 Freescale Semiconductor
MAP-BGA Package Mechanical Drawing
3.4 MAP-BGA Package Mechanical Drawing
Notes: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
DIM A A1 A2 b D E e
Millimeters MIN MAX 1.6 1.9 0.50 0.70 1.16 REF 0.60 0.90 21.00 BSC 21.00 BSC 1.27 BSC
Figure 3-6.
DSP56301 Mechanical Information, 252-pin MAP-BGA Package
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 3-23
Packaging
DSP56301 Technical Data, Rev. 10 3-24 Freescale Semiconductor
Design Considerations
4.1 Thermal Design Considerations
An estimate of the chip junction temperature, TJ, in C can be obtained from this equation: Equation 1: TJ = T A + ( P D x R JA ) Where: TA RJA PD = = = ambient temperature C package junction-to-ambient thermal resistance C/W power dissipation in package
4
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a caseto-ambient thermal resistance, as in this equation: Equation 2: R JA = RJC + R CA Where: RJA RJC RCA = = = package junction-to-ambient thermal resistance C/W package junction-to-case thermal resistance C/W package case-to-ambient thermal resistance C/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 4-1
*
Design Considerations
*
If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is computed from the value obtained by the equation (TJ - TT)/PD.
As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
4.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC).
Use the following list of recommendations to ensure correct DSP operation. * * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. Use at least a four-layer PCB with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (TRST, TMS, DE). Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins. The following pins must be asserted after power-up: RESET and TRST.
DSP56301 Technical Data, Rev. 10 4-2 Freescale Semiconductor
*
* * *
Power Consumption Considerations
* * *
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.5 V.
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this formula: Equation 3: I = C x V x f Where: C V f = = = node/pin capacitance voltage swing frequency of node/pin toggle
Example 1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4.
- 12
Equation 4:
I = 50 x 10
x 3.3 x 33 x 10 = 5.48 mA
6
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on bestcase operation conditions--not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for applications that require very low current consumption:
1. 2. 3. 4. 5. 6. 7.
Set the EBD bit when you are not accessing external memory. Minimize external memory accesses, and use internal memory accesses. Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. Disable unused pin activity (for example, CLKOUT, XTAL).
One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current-per-MIPS value.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor 4-3
Design Considerations
Equation 5: Where: ItypF2 ItypF1 F2 F1 = = = =
I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 )
current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2)
Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
4.4 PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
4.4.1
Phase Skew Performance
The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 2-2, External Clock Timing, on page -5 for input frequencies greater than 15 MHz and the MF 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between -1.4 ns and +3.2 ns.
4.4.2
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than 2 ns.
4.4.3
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5 per cent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 per cent and approximately 2 per cent. For large MF (MF > 500), the frequency jitter is 2-3 per cent.
4.5 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.
DSP56301 Technical Data, Rev. 10 4-4 Freescale Semiconductor
Power Consumption Benchmark
A
The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;************************************************************************** ;************************************************************************** ;* * ;* CHECKS Typical Power Consumption * ;* * ;************************************************************************** page 200,55,0,0,0 nolist I_VEC EQU$000000; Interrupt vectors for program debug only START EQU$8000 ; MAIN (external) program starting address INT_PROG EQU$100 ; INTERNAL program memory starting address INT_XDAT EQU$0 ; INTERNAL X-data memory starting address INT_YDAT EQU$0 ; INTERNAL Y-data memory starting address INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Area 2 : 0 w.s (SSRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL; XTAL disable ; PLL enable ; CLKOUT disable ; ;Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 P:START
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-1
Power Consumption Benchmark do #(XDAT_END-XDAT_START),XLOAD_LOOP move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP ; ;Load the Y-data ; move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr
; ebd
#60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
XDAT_START ; org dc dc dc dc dc dc dc dc dc dc
x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 DSP56301 Technical Data, Rev. 10
A-2
Freescale Semiconductor
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc
$6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-3
Power Consumption Benchmark dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF
DSP56301 Technical Data, Rev. 10 A-4 Freescale Semiconductor
dc $6162BC dc $E4A245 YDAT_END ;************************************************************************** ; ; EQUATES for DSP56301 I/O registers and ports ; Reference: DSP56301 Specifications Revision 3.00 ; ; Last update: November 15 1993 ; Changes: GPIO for ports C,D and E, ; HI32 ; DMA status reg ; PLL control reg ; AAR ; SCI registers address ; SSI registers addr. + split TSR from SSISR ; December 19 1993 (cosmetic - page and opt directives) ; August 9 1994 ESSI and SCI control registers bit update ; ;************************************************************************** page opt ioequ ident 132,55,0,0,0 mex 1,0
;-----------------------------------------------------------------------; ; EQUATES for I/O Port Programming ; ;-----------------------------------------------------------------------; M_DATH M_DIRH M_PCRC M_PRRC M_PDRC M_PCRD M_PRRD M_PDRD M_PCRE M_PRRE M_PDRE M_OGDB Register Addresses EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $FFFFCF ; Host port GPIO data Register $FFFFCE; Host port GPIO direction Register $FFFFBF; Port C Control Register $FFFFBE; Port C Direction Register $FFFFBD ; Port C GPIO Data Register $FFFFAF ; Port D Control register $FFFFAE ; Port D Direction Data Register $FFFFAD; Port D GPIO Data Register $FFFF9F; Port E Control register $FFFF9E; Port E Direction Register $FFFF9D; Port E Data Register $FFFFFC; OnCE GDB Register
;-----------------------------------------------------------------------; ; EQUATES for Host Interface ; ;-----------------------------------------------------------------------; Register Addresses EQU EQU EQU EQU $FFFFCD ; DSP SLAVE TRANSMIT DATA FIFO (DTXS) $FFFFCC; DSP MASTER TRANSMIT DATA FIFO (DTXM) $FFFFCB; DSP RECEIVE DATA FIFO (DRXR) $FFFFCA; DSP PCI STATUS REGISTER (DPSR)
M_DTXS M_DTXM M_DRXR M_DPSR
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-5
Power Consumption Benchmark M_DSR EQU $FFFFC9; DSP STATUS REGISTER (DSR) M_DPAR EQU $FFFFC8; DSP PCI ADDRESS REGISTER (DPAR) M_DPMC EQU $FFFFC7; DSP PCI MASTER CONTROL REGISTER (DPMC) M_DPCR EQU $FFFFC6; DSP PCI CONTROL REGISTER (DPCR) M_DCTR EQU $FFFFC5 ; DSP CONTROL REGISTER (DCTR) ; Host Control Register Bit Flags
M_HCIE EQU 0 ; Host Command Interrupt Enable M_STIE EQU 1 ; Slave Transmit Interrupt Enable M_SRIE EQU 2 ; Slave Receive Interrupt Enable M_HF35 EQU $38 ; Host Flags 5-3 Mask M_HF3 EQU 3 ; Host Flag 3 M_HF4 EQU 4 ; Host Flag 4 M_HF5 EQU 5 ; Host Flag 5 M_HINT EQU 6 ; Host Interrupt A M_HDSM EQU 13 ; Host Data Strobe Mode M_HRWP EQU 14 ; Host RD/WR Polarity M_HTAP EQU 15 ; Host Transfer Acknowledge Polarity M_HDRP EQU 16 ; Host Dma Request Polarity M_HRSP EQU 17 ; Host Reset Polarity M_HIRP EQU 18 ; Host Interrupt Request Polarity M_HIRC EQU 19 ; Host Interupt Request Control M_HM0 EQU 20 ; Host Interface Mode M_HM1 EQU 21 ; Host Interface Mode M_HM2 EQU 22 ; Host Interface Mode M_HM EQU $700000 ; Host Interface Mode Mask ; Host PCI Control Register Bit Flags PCI Master Transmit Interrupt Enable PCI Master Receive Interrupt Enable PCI Master Address Interrupt Enable PCI Parity Error Interrupt Enable PCI Transaction Abort Interrupt Enable PCI Transaction Termination Interrupt Enable ; PCI Transfer Complete Interrupt Enable Clear Transmitter Master Transfer Terminate HSERR~ Force Master Access Counter Enable Master Wait States Disable Receive Buffer Lock Enable Insert Address Enable
M_PMTIE EQU 1 ; M_PMRIE EQU 2 ; M_PMAIE EQU 4 ; M_PPEIE EQU 5 ; M_PTAIE EQU 7 ; M_PTTIE EQU 9 ; M_PTCIE EQU 12 M_CLRT EQU 14 ; M_MTT EQU 15 ; M_SERF EQU 16 ; M_MACE EQU 18 ; M_MWSD EQU 19 ; M_RBLE EQU 20 ; M_IAE EQU 21 ; ;
Host PCI Master Control Register Bit Flags
M_ARH EQU $00ffff; DSP PCI Transaction Address (High) M_BL EQU $3f0000; PCI Data Burst Length M_FC EQU $c00000; Data Transfer Format Control ; Host PCI Address Register Bit Flags
M_ARL EQU $00ffff; DSP PCI Transaction Address (Low) M_C EQU $0f0000; PCI Bus Command M_BE EQU $f00000; PCI Byte Enables ; DSP Status Register Bit Flags ; Host Command pending
M_HCP EQU 0
DSP56301 Technical Data, Rev. 10 A-6 Freescale Semiconductor
M_STRQ EQU 1 ; M_SRRQ EQU 2 ; M_HF02 EQU $38 ; M_HF0 EQU 3 ; M_HF1 EQU 4 ; M_HF2 EQU 5 ; ;
Slave Transmit Data Request Slave Receive Data Request Host Flag 0-2 Mask Host Flag 0 Host Flag 1 Host Flag 2
DSP PCI Status Register Bit Flags
M_MWS EQU 0 ; PCI Master Wait States M_MTRQ EQU 1 ; PCI Master Transmit Data Request M_MRRQ EQU 2 ; PCI Master Receive Data Request M_MARQ EQU 4 ; PCI Master Address Request M_APER EQU 5 ; PCI Address Parity Error M_DPER EQU 6 ; PCI Data Parity Error M_MAB EQU 7 ; PCI Master Abort M_TAB EQU 8 ; PCI Target Abort M_TDIS EQU 9 ; PCI Target Disconnect M_TRTY EQU 10 ; PCI Target Retry M_TO EQU 11 ; PCI Time Out Termination M_RDC EQU $3F0000; Remaining Data Count Mask (RDC5-RDC0) M_RDC0 EQU 16 ; Remaining Data Count 0 M_RDC1 EQU 17 ; Remaining Data Count 1 M_RDC2 EQU 18 ; Remaining Data Count 2 M_RDC3 EQU 19 ; Remaining Data Count 3 M_RDC4 EQU 20 ; Remaining Data Count 4 M_RDC5 EQU 21 ; Remaining Data Count 5 M_HACT EQU 23 ; Hi32 Active
;-----------------------------------------------------------------------; ; EQUATES for Serial Communications Interface (SCI) ; ;-----------------------------------------------------------------------; Register Addresses
M_STXH EQU $FFFF97; SCI Transmit Data Register (high) M_STXM EQU $FFFF96; SCI Transmit Data Register (middle) M_STXL EQU $FFFF95; SCI Transmit Data Register (low) M_SRXH EQU $FFFF9A; SCI Receive Data Register (high) M_SRXM EQU $FFFF99; SCI Receive Data Register (middle) M_SRXL EQU $FFFF98; SCI Receive Data Register (low) M_STXA EQU $FFFF94; SCI Transmit Address Register M_SCR EQU $FFFF9C; SCI Control Register M_SSR EQU $FFFF93; SCI Status Register M_SCCR EQU $FFFF9B; SCI Clock Control Register ; SCI Control Register Bit Flags ; Word Select Mask (WDS0-WDS3) ; Word Select 0 ; Word Select 1 ; Word Select 2 ; SCI Shift Direction ; Send Break ; Wakeup Mode Select ; Receiver Wakeup Enable ; Wired-OR Mode Select
M_WDS EQU $7 M_WDS0 EQU 0 M_WDS1 EQU 1 M_WDS2 EQU 2 M_SSFTD EQU 3 M_SBK EQU 4 M_WAKE EQU 5 M_RWU EQU 6 M_WOMS EQU 7
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-7
Power Consumption Benchmark M_SCRE EQU 8 M_SCTE EQU 9 M_ILIE EQU 10 M_SCRIE EQU 11 M_SCTIE EQU 12 M_TMIE EQU 13 M_TIR EQU 14 M_SCKP EQU 15 M_REIE EQU 16 ; ; SCI Receiver Enable ; SCI Transmitter Enable ; Idle Line Interrupt Enable ; SCI Receive Interrupt Enable ; SCI Transmit Interrupt Enable ; Timer Interrupt Enable ; Timer Interrupt Rate ; SCI Clock Polarity ; SCI Error Interrupt Enable (REIE)
SCI Status Register Bit Flags 0 1 2 3 ; ; ; ; ; Transmitter Empty ; Transmit Data Register Empty ; Receive Data Register Full ; Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 (R8) Address
M_TRNE EQU M_TDRE EQU M_RDRF EQU M_IDLE EQU M_OR EQU 4 M_PE EQU 5 M_FE EQU 6 M_R8 EQU 7 ;
SCI Clock Control Register ; Clock Divider Mask (CD0-CD11) ; Clock Out Divider ; Clock Prescaler ; Receive Clock Mode Source Bit ; Transmit Clock Source Bit
M_CD EQU $FFF M_COD EQU 12 M_SCP EQU 13 M_RCM EQU 14 M_TCM EQU 15
;-----------------------------------------------------------------------; ; EQUATES for Synchronous Serial Interface (SSI) ; ;-----------------------------------------------------------------------; ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC; SSI0 Transmit Data Register 0 M_TX01 EQU $FFFFBB; SSIO Transmit Data Register 1 M_TX02 EQU $FFFFBA; SSIO Transmit Data Register 2 M_TSR0 EQU $FFFFB9; SSI0 Time Slot Register M_RX0 EQU $FFFFB8; SSI0 Receive Data Register M_SSISR0 EQU $FFFFB7; SSI0 Status Register M_CRB0 EQU $FFFFB6; SSI0 Control Register B M_CRA0 EQU $FFFFB5; SSI0 Control Register A M_TSMA0 EQU $FFFFB4; SSI0 Transmit Slot Mask Register A M_TSMB0 EQU $FFFFB3; SSI0 Transmit Slot Mask Register B M_RSMA0 EQU $FFFFB2; SSI0 Receive Slot Mask Register A M_RSMB0 EQU $FFFFB1; SSI0 Receive Slot Mask Register B ; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC; SSI1 Transmit Data Register 0 M_TX11 EQU $FFFFAB; SSI1 Transmit Data Register 1 M_TX12 EQU $FFFFAA; SSI1 Transmit Data Register 2 M_TSR1 EQU $FFFFA9; SSI1 Time Slot Register M_RX1 EQU $FFFFA8; SSI1 Receive Data Register M_SSISR1 EQU $FFFFA7; SSI1 Status Register M_CRB1 EQU $FFFFA6; SSI1 Control Register B M_CRA1 EQU $FFFFA5; SSI1 Control Register A M_TSMA1 EQU $FFFFA4; SSI1 Transmit Slot Mask Register A
DSP56301 Technical Data, Rev. 10 A-8 Freescale Semiconductor
M_TSMB1 EQU $FFFFA3; SSI1 Transmit Slot Mask Register B M_RSMA1 EQU $FFFFA2; SSI1 Receive Slot Mask Register A M_RSMB1 EQU $FFFFA1; SSI1 Receive Slot Mask Register B ; SSI Control Register A Bit Flags
M_PM EQU $FF ; Prescale Modulus Select Mask (PM0-PM7) M_PSR EQU 11 ; Prescaler Range M_DC EQU $1F000 ; Frame Rate Divider Control Mask (DC0-DC7) M_ALC EQU 18 ; Alignment Control (ALC) M_WL EQU $380000; Word Length Control Mask (WL0-WL7) M_SSC1 EQU 22 ; Select SC1 as TR #0 drive enable (SSC1) ; SSI Control Register B Bit Flags
M_OF EQU $3 ; Serial Output Flag Mask M_OF0 EQU 0 ; Serial Output Flag 0 M_OF1 EQU 1 ; Serial Output Flag 1 M_SCD EQU $1C ; Serial Control Direction Mask M_SCD0 EQU 2 ; Serial Control 0 Direction M_SCD1 EQU 3 ; Serial Control 1 Direction M_SCD2 EQU 4 ; Serial Control 2 Direction M_SCKD EQU 5 ; Clock Source Direction M_SHFD EQU 6 ; Shift Direction M_FSL EQU $180 ; Frame Sync Length Mask (FSL0-FSL1) M_FSL0 EQU 7 ; Frame Sync Length 0 M_FSL1 EQU 8 ; Frame Sync Length 1 M_FSR EQU 9 ; Frame Sync Relative Timing M_FSP EQU 10 ; Frame Sync Polarity M_CKP EQU 11 ; Clock Polarity M_SYN EQU 12 ; Sync/Async Control M_MOD EQU 13 ; SSI Mode Select M_SSTE EQU $1C000; SSI Transmit enable Mask M_SSTE2 EQU 14 ; SSI Transmit #2 Enable M_SSTE1 EQU 15 ; SSI Transmit #1 Enable M_SSTE0 EQU 16 ; SSI Transmit #0 Enable M_SSRE EQU 17 ; SSI Receive Enable M_SSTIE EQU 18 ; SSI Transmit Interrupt Enable M_SSRIE EQU 19 ; SSI Receive Interrupt Enable M_STLIE EQU 20 ; SSI Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 ; SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 ; SSI Transmit Error Interrupt Enable M_SREIE EQU 23 ; SSI Receive Error Interrupt Enable
;
SSI Status Register Bit Flags ; Serial Input Flag Mask ; Serial Input Flag 0 ; Serial Input Flag 1 ; Transmit Frame Sync Flag ; Receive Frame Sync Flag ; Transmitter Underrun Error FLag ; Receiver Overrun Error Flag ; Transmit Data Register Empty ; Receive Data Register Full
M_IF EQU $3 M_IF0 EQU 0 M_IF1 EQU 1 M_TFS EQU 2 M_RFS EQU 3 M_TUE EQU 4 M_ROE EQU 5 M_TDE EQU 6 M_RDF EQU 7 ;
SSI Transmit Slot Mask Register A ; SSI Transmit Slot Bits Mask A (TS0-TS15)
M_SSTSA EQU $FFFF
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-9
Power Consumption Benchmark
;
SSI Transmit Slot Mask Register B ; SSI Transmit Slot Bits Mask B (TS16-TS31)
M_SSTSB EQU $FFFF ;
SSI Receive Slot Mask Register A ; SSI Receive Slot Bits Mask A (RS0-RS15)
M_SSRSA EQU $FFFF ;
SSI Receive Slot Mask Register B ; SSI Receive Slot Bits Mask B (RS16-RS31)
M_SSRSB EQU $FFFF
;-----------------------------------------------------------------------; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------
;
Register Addresses
M_IPRC EQU $FFFFFF; Interrupt Priority Register Core M_IPRP EQU $FFFFFE; Interrupt Priority Register Peripheral ; Interrupt Priority Register Core (IPRC)
M_IAL EQU $7 ; IRQA Mode Mask M_IAL0 EQU 0 ; IRQA Mode Interrupt Priority Level (low) M_IAL1 EQU 1 ; IRQA Mode Interrupt Priority Level (high) M_IAL2 EQU 2 ; IRQA Mode Trigger Mode M_IBL EQU $38 ; IRQB Mode Mask M_IBL0 EQU 3 ; IRQB Mode Interrupt Priority Level (low) M_IBL1 EQU 4 ; IRQB Mode Interrupt Priority Level (high) M_IBL2 EQU 5 ; IRQB Mode Trigger Mode M_ICL EQU $1C0 ; IRQC Mode Mask M_ICL0 EQU 6 ; IRQC Mode Interrupt Priority Level (low) M_ICL1 EQU 7 ; IRQC Mode Interrupt Priority Level (high) M_ICL2 EQU 8 ; IRQC Mode Trigger Mode M_IDL EQU $E00 ; IRQD Mode Mask M_IDL0 EQU 9 ; IRQD Mode Interrupt Priority Level (low) M_IDL1 EQU 10 ; IRQD Mode Interrupt Priority Level (high) M_IDL2 EQU 11 ; IRQD Mode Trigger Mode M_D0L EQU $3000 ; DMA0 Interrupt priority Level Mask M_D0L0 EQU 12 ; DMA0 Interrupt Priority Level (low) M_D0L1 EQU 13 ; DMA0 Interrupt Priority Level (high) M_D1L EQU $C000 ; DMA1 Interrupt Priority Level Mask M_D1L0 EQU 14 ; DMA1 Interrupt Priority Level (low) M_D1L1 EQU 15 ; DMA1 Interrupt Priority Level (high) M_D2L EQU $30000 ; DMA2 Interrupt priority Level Mask M_D2L0 EQU 16 ; DMA2 Interrupt Priority Level (low) M_D2L1 EQU 17 ; DMA2 Interrupt Priority Level (high) M_D3L EQU $C0000 ; DMA3 Interrupt Priority Level Mask M_D3L0 EQU 18 ; DMA3 Interrupt Priority Level (low) M_D3L1 EQU 19 ; DMA3 Interrupt Priority Level (high) M_D4L EQU $300000; DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 ; DMA4 Interrupt Priority Level (low) M_D4L1 EQU 21 ; DMA4 Interrupt Priority Level (high)
DSP56301 Technical Data, Rev. 10 A-10 Freescale Semiconductor
M_D5L EQU $C00000; DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 ; DMA5 Interrupt Priority Level (low) M_D5L1 EQU 23 ; DMA5 Interrupt Priority Level (high)
;
Interrupt Priority Register Peripheral (IPRP) ; Host Interrupt Priority Level Mask ; Host Interrupt Priority Level (low) ; Host Interrupt Priority Level (high) ; SSI0 Interrupt Priority Level Mask ; SSI0 Interrupt Priority Level (low) ; SSI0 Interrupt Priority Level (high) ; SSI1 Interrupt Priority Level Mask ; SSI1 Interrupt Priority Level (low) ; SSI1 Interrupt Priority Level (high) ; SCI Interrupt Priority Level Mask ; SCI Interrupt Priority Level (low) ; SCI Interrupt Priority Level (high) ; TIMER Interrupt Priority Level Mask ; TIMER Interrupt Priority Level (low) ; TIMER Interrupt Priority Level (high)
M_HPL EQU $3 M_HPL0 EQU 0 M_HPL1 EQU 1 M_S0L EQU $C M_S0L0 EQU 2 M_S0L1 EQU 3 M_S1L EQU $30 M_S1L0 EQU 4 M_S1L1 EQU 5 M_SCL EQU $C0 M_SCL0 EQU 6 M_SCL1 EQU 7 M_T0L EQU $300 M_T0L0 EQU 8 M_T0L1 EQU 9
;-----------------------------------------------------------------------; ; EQUATES for TIMER ; ;-----------------------------------------------------------------------; Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F; TIMER0 Control/Status Register M_TLR0 EQU $FFFF8E; TIMER0 Load Reg M_TCPR0 EQU $FFFF8D; TIMER0 Compare Register M_TCR0 EQU $FFFF8C ; TIMER0 Count Register ; Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B; TIMER1 Control/Status Register M_TLR1 EQU $FFFF8A; TIMER1 Load Reg M_TCPR1 EQU $FFFF89; TIMER1 Compare Register M_TCR1 EQU $FFFF88; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87; TIMER2 Control/Status Register M_TLR2 EQU $FFFF8; TIMER2 Load Reg M_TCPR2 EQU $FFFF85; TIMER2 Compare Register M_TCR2 EQU $FFFF84 ; TIMER2 Count Register M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags ; Timer Enable ; Timer Overflow Interrupt Enable ; Timer Compare Interrupt Enable
M_TE EQU 0 M_TOIE EQU 1 M_TCIE EQU 2
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-11
Power Consumption Benchmark M_TC EQU $F0 M_INV EQU 8 M_TRM EQU 9 M_DIR EQU 11 M_DI EQU 12 M_DO EQU 13 M_PCE EQU 15 M_TOF EQU 20 M_TCF EQU 21 ; ; Timer Control Mask (TC0-TC3) ; Inverter Bit ; Timer Restart Mode ; Direction Bit ; Data Input ; Data Output ; Prescaled Clock Enable ; Timer Overflow Flag ; Timer Compare Flag
Timer Prescaler Register Bit Flags
M_PS EQU $600000 ; Prescaler Source Mask M_PS0 EQU 21 M_PS1 EQU 22 ; M_TC0 M_TC1 M_TC2 M_TC3 Timer Control Bits EQU 4 ; Timer Control EQU 5 ; Timer Control EQU 6 ; Timer Control EQU 7 ; Timer Control
0 1 2 3
;-----------------------------------------------------------------------; ; EQUATES for Direct Memory Access (DMA) ; ;-----------------------------------------------------------------------; M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 Register Addresses Of DMA EQU $FFFFF4; DMA Status Register EQU $FFFFF3; DMA Offset Register EQU $FFFFF2; DMA Offset Register EQU $FFFFF1; DMA Offset Register EQU $FFFFF0; DMA Offset Register
0 1 2 3
; M_DSR0 M_DDR0 M_DCO0 M_DCR0 ; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; M_DSR2 M_DDR2 M_DCO2 M_DCR2 ;
Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF; $FFFFEE; $FFFFED; $FFFFEC; DMA0 DMA0 DMA0 DMA0 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB; $FFFFEA; $FFFFE9; $FFFFE8; DMA1 DMA1 DMA1 DMA1 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA2 EQU EQU EQU EQU $FFFFE7; $FFFFE6; $FFFFE5; $FFFFE4; DMA2 DMA2 DMA2 DMA2 Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA4
DSP56301 Technical Data, Rev. 10 A-12 Freescale Semiconductor
M_DSR3 M_DDR3 M_DCO3 M_DCR3 ;
EQU EQU EQU EQU
$FFFFE3; $FFFFE2; $FFFFE1; $FFFFE0;
DMA3 DMA3 DMA3 DMA3
Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA4
M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; M_DSR5 M_DDR5 M_DCO5 M_DCR5 ;
EQU EQU EQU EQU
$FFFFDF; $FFFFDE; $FFFFDD; $FFFFDC;
DMA4 DMA4 DMA4 DMA4
Source Address Register Destination Address Register Counter Control Register
Register Addresses Of DMA5 EQU EQU EQU EQU $FFFFDB; $FFFFDA; $FFFFD9; $FFFFD8; DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register
DMA Control Register
M_DSS EQU $3 ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 EQU 0 ; DMA Source Memory space 0 M_DSS1 EQU 1 ; DMA Source Memory space 1 M_DDS EQU $C ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 EQU 2 ; DMA Destination Memory Space 0 M_DDS1 EQU 3 ; DMA Destination Memory Space 1 M_DAM EQU $3F0 ; DMA Address Mode Mask (DAM5-DAM0) M_DAM0 EQU 4 ; DMA Address Mode 0 M_DAM1 EQU 5 ; DMA Address Mode 1 M_DAM2 EQU 6 ; DMA Address Mode 2 M_DAM3 EQU 7 ; DMA Address Mode 3 M_DAM4 EQU 8 ; DMA Address Mode 4 M_DAM5 EQU 9 ; DMA Address Mode 5 M_D3D EQU 10 ; DMA Three Dimensional Mode M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4) M_DCON EQU 16 ; DMA Continuous Mode M_DPR EQU $60000; DMA Channel Priority M_DPR0 EQU 17 ; DMA Channel Priority Level (low) M_DPR1 EQU 18 ; DMA Channel Priority Level (high) M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0) M_DTM0 EQU 19 ; DMA Transfer Mode 0 M_DTM1 EQU 20 ; DMA Transfer Mode 1 M_DTM2 EQU 21 ; DMA Transfer Mode 2 M_DIE EQU 22 ; DMA Interrupt Enable bit M_DE EQU 23 ; DMA Channel Enable bit ; DMA Status Register Channel Transfer Done Status MASK (DTD0-DTD5) ; DMA Channel Transfer Done Status 0 ; DMA Channel Transfer Done Status 1 ; DMA Channel Transfer Done Status 2 ; DMA Channel Transfer Done Status 3 ; DMA Channel Transfer Done Status 4 ; DMA Channel Transfer Done Status 5 DMA Active State DMA Active Channel Mask (DCH0-DCH2) DMA Active Channel 0
M_DTD EQU $3F ; M_DTD0 EQU 0 M_DTD1 EQU 1 M_DTD2 EQU 2 M_DTD3 EQU 3 M_DTD4 EQU 4 M_DTD5 EQU 5 M_DACT EQU 8 ; M_DCH EQU $E00 ; M_DCH0 EQU 9 ;
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-13
Power Consumption Benchmark M_DCH1 EQU 10 ; DMA Active Channel 1 M_DCH2 EQU 11 ; DMA Active Channel 2
;-----------------------------------------------------------------------; ; EQUATES for Phase Lock Loop (PLL) ; ;-----------------------------------------------------------------------; Register Addresses Of PLL
M_PCTL EQU $FFFFFD; PLL Control Register ; PLL Control Register
M_MF EQU $FFF ; Multiplication Factor Bits Mask (MF0-MF11) M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2) M_XTLR EQU 15 ; XTAL Range select bit M_XTLD EQU 16 ; XTAL Disable Bit M_PSTP EQU 17 ; STOP Processing State Bit M_PEN EQU 18 ; PLL Enable Bit M_PCOD EQU 19 ; PLL Clock Output Disable Bit M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)
;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;-----------------------------------------------------------------------; Register Addresses Of BIU
M_BCR EQU $FFFFFB; Bus Control Register M_DCR EQU $FFFFFA; DRAM Control Register M_AAR0 EQU $FFFFF9; Address Attribute Register M_AAR1 EQU $FFFFF8; Address Attribute Register M_AAR2 EQU $FFFFF7; Address Attribute Register M_AAR3 EQU $FFFFF6; Address Attribute Register M_IDR EQU $FFFFF5; ID Register ; Bus Control Register
0 1 2 3
M_BA0W EQU $1F ; Area 0 Wait Control Mask (BA0W0-BA0W4) M_BA1W EQU $3E0 ; Area 1 Wait Control Mask (BA1W0-BA14) M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2) M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3) M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4) M_BBS EQU 21 ; Bus State M_BLH EQU 22 ; Bus Lock Hold M_BRH EQU 23 ; Bus Request Hold ; DRAM Control Register ; In Page Wait States Bits Mask (BCW0-BCW1) ; Out Of Page Wait States Bits Mask (BRW0-BRW1) ; DRAM Page Size Bits Mask (BPS0-BPS1) ; Page Logic Enable
M_BCW EQU $3 M_BRW EQU $C M_BPS EQU $300 M_BPLE EQU 11
DSP56301 Technical Data, Rev. 10 A-14 Freescale Semiconductor
M_BME EQU 12 ; Mastership Enable M_BRE EQU 13 ; Refresh Enable M_BSTR EQU 14 ; Software Triggered Refresh M_BRF EQU $7F8000; Refresh Rate Bits Mask (BRF0-BRF7) M_BRP EQU 23 ; Refresh prescaler ; Address Attribute Registers
M_BAT EQU $3 ; External Access Type and Pin Definition Bits Mask (BAT0-BAT1) M_BAAP EQU 2 ; Address Attribute Pin Polarity M_BPEN EQU 3 ; Program Space Enable M_BXEN EQU 4 ; X Data Space Enable M_BYEN EQU 5 ; Y Data Space Enable M_BAM EQU 6 ; Address Muxing M_BPAC EQU 7 ; Packing Enable M_BNC EQU $F00 ; Number of Address Bits to Compare Mask (BNC0-BNC3) M_BAC EQU $FFF000; Address to Compare Bits Mask (BAC0-BAC11) ; control and status bits in SR
M_CP EQU $c00000 ; mask for CORE-DMA priority bits in SR M_CA EQU 0 ; Carry M_V EQU 1 ; Overflow M_Z EQU 2 ; Zero M_N EQU 3 ; Negative M_U EQU 4 ; Unnormalized M_E EQU 5 ; Extension M_L EQU 6 ; Limit M_S EQU 7 ; Scaling Bit M_I0 EQU 8 ; Interupt Mask Bit 0 M_I1 EQU 9 ; Interupt Mask Bit 1 M_S0 EQU 10 ; Scaling Mode Bit 0 M_S1 EQU 11 ; Scaling Mode Bit 1 M_SC EQU 13 ; Sixteen_Bit Compatibility M_DM EQU 14 ; Double Precision Multiply M_LF EQU 15 ; DO-Loop Flag M_FV EQU 16 ; DO-Forever Flag M_SA EQU 17 ; Sixteen-Bit Arithmetic M_CE EQU 19 ; Instruction Cache Enable M_SM EQU 20 ; Arithmetic Saturation M_RM EQU 21 ; Rounding Mode M_CP0 EQU22 ; bit 0 of priority bits in SR M_CP1 EQU 23 ; bit 1 of priority bits in SR ; control and status bits in OMR M_CDP EQU$300 ; mask for CORE-DMA priority bits in OMR M_MA EQU 0 ; Operating Mode A M_MB EQU 1 ; Operating Mode B M_MC EQU 2 ; Operating Mode C M_MD EQU 3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR.
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-15
Power Consumption Benchmark M_WRP EQU 19 ; Extended WRaP flag in OMR. M_SEN EQU 20 ; Stack Extension Enable bit in OMR. ;************************************************************************* ; ; EQUATES for DSP56301 interrupts ; Reference: DSP56301 Specifications Revision 3.00 ; ; Last update: November 15 1993 (Debug request & HI32 interrupts) ; December 19 1993 (cosmetic - page and opt directives) ; August 16 1994 (change interrupt addresses to be relative to I_VEC) ; ;************************************************************************* page opt intequ ident 132,55,0,0,0 mex 1,0
;
I_VEC
if @DEF(I_VEC) ;leave user definition as is. else equ $0 endif
;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5
;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow
DSP56301 Technical Data, Rev. 10 A-16 Freescale Semiconductor
I_TIM1C I_TIM1OF I_TIM2C I_TIM2OF
EQU EQU EQU EQU
I_VEC+$28 I_VEC+$2A I_VEC+$2C I_VEC+$2E
; ; ; ;
TIMER TIMER TIMER TIMER
1 1 2 2
compare overflow compare overflow
;-----------------------------------------------------------------------; ESSI Interrupts ;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data With Exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data With Exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data With Exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data With Exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ;-----------------------------------------------------------------------; SCI Interrupts ;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ;-----------------------------------------------------------------------; HOST Interrupts ;-----------------------------------------------------------------------I_HPTT EQU I_VEC+$60 ; Host PCI Transaction Termination I_HPTA EQU I_VEC+$62 ; Host PCI Transaction Abort I_HPPE EQU I_VEC+$64 ; Host PCI Parity Error I_HPTC EQU I_VEC+$66 ; Host PCI Transfer Complete I_HPMR EQU I_VEC+$68 ; Host PCI Master Receive I_HSR EQU I_VEC+$6A ; Host Slave Receive I_HPMT EQU I_VEC+$6C ; Host PCI Master Transmit I_HST EQU I_VEC+$6E ; Host Slave Transmit I_HPMA EQU I_VEC+$70 ; Host PCI Master Address I_HCNMI EQU I_VEC+$72 ; Host Command/Host NMI (Default) ;-----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
DSP56301 Technical Data, Rev. 10 Freescale Semiconductor A-17
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core Frequency (MHz) 80
Part DSP56301
Supply Voltage 3.3 V
Package Type Thin Quad Flat Pack (TQFP)
Pin Count 208
Solder Spheres Lead-free Lead-bearing
Order Number DSP56301AG80 DSP56301PW80 DSP56301AG100 DSP56301PW100 DSP56301VL80 DSP56301VF80 DSP56301VL100 DSP56301VF100
100
Lead-free Lead-bearing
Molded Array Process-Ball Grid Array (MAP-BGA)
252
80
Lead-free Lead-bearing
100
Lead-free Lead-bearing
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Document Order No.: DSP56301 Rev. 10 7/2006

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